<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE article PUBLIC "-//TaxonX//DTD Taxonomic Treatment Publishing DTD v0 20100105//EN" "../../nlm/tax-treatment-NS0.dtd">
<article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:tp="http://www.plazi.org/taxpub" article-type="research-article" dtd-version="3.0" xml:lang="en">
  <front>
    <journal-meta>
      <journal-id journal-id-type="publisher-id">109</journal-id>
      <journal-id journal-id-type="index">urn:lsid:arphahub.com:pub:3dc5f44e-8666-58db-bc76-a455210e8891</journal-id>
      <journal-title-group>
        <journal-title xml:lang="en">JUCS - Journal of Universal Computer Science</journal-title>
        <abbrev-journal-title xml:lang="en">jucs</abbrev-journal-title>
      </journal-title-group>
      <issn pub-type="ppub">0948-695X</issn>
      <issn pub-type="epub">0948-6968</issn>
      <publisher>
        <publisher-name>Journal of Universal Computer Science</publisher-name>
      </publisher>
    </journal-meta>
    <article-meta>
      <article-id pub-id-type="doi">10.3217/jucs-024-12-1776</article-id>
      <article-id pub-id-type="publisher-id">23789</article-id>
      <article-categories>
        <subj-group subj-group-type="heading">
          <subject>Research Article</subject>
        </subj-group>
        <subj-group subj-group-type="scientific_subject">
          <subject>B.6.3 - Design Aids</subject>
          <subject>B.8.1 - Reliability</subject>
          <subject> Testing</subject>
          <subject> and Fault-Tolerance</subject>
          <subject>C.4 - PERFORMANCE OF SYSTEMS</subject>
          <subject>C.5 - COMPUTER SYSTEM IMPLEMENTATION</subject>
          <subject>J.6 - COMPUTER-AIDED ENGINEERING</subject>
        </subj-group>
      </article-categories>
      <title-group>
        <article-title>Dynamic Estimation of Temporary Failure in SoC FPGAs for Heterogeneous Applications</article-title>
      </title-group>
      <contrib-group content-type="authors">
        <contrib contrib-type="author" corresp="yes">
          <name name-style="western">
            <surname>Kokila</surname>
            <given-names>J.</given-names>
          </name>
          <email xlink:type="simple">406114002@nitt.edu</email>
          <xref ref-type="aff" rid="A1">1</xref>
        </contrib>
        <contrib contrib-type="author" corresp="no">
          <name name-style="western">
            <surname>Ramasubramanian</surname>
            <given-names>N.</given-names>
          </name>
          <xref ref-type="aff" rid="A1">1</xref>
        </contrib>
        <contrib contrib-type="author" corresp="no">
          <name name-style="western">
            <surname>Thamma</surname>
            <given-names>Ravindra</given-names>
          </name>
          <xref ref-type="aff" rid="A2">2</xref>
        </contrib>
      </contrib-group>
      <aff id="A1">
        <label>1</label>
        <addr-line content-type="verbatim">National Institute of Technology, Tiruchirappalli, India</addr-line>
        <institution>National Institute of Technology</institution>
        <addr-line content-type="city">Tiruchirappalli</addr-line>
        <country>India</country>
      </aff>
      <aff id="A2">
        <label>2</label>
        <addr-line content-type="verbatim">Central Connecticut State University, New Britain, United States of America</addr-line>
        <institution>Central Connecticut State University</institution>
        <addr-line content-type="city">New Britain</addr-line>
        <country>United States of America</country>
      </aff>
      <author-notes>
        <fn fn-type="corresp">
          <p>Corresponding author: J. Kokila (<email xlink:type="simple">406114002@nitt.edu</email>).</p>
        </fn>
        <fn fn-type="edited-by">
          <p>Academic editor: </p>
        </fn>
      </author-notes>
      <pub-date pub-type="collection">
        <year>2018</year>
      </pub-date>
      <pub-date pub-type="epub">
        <day>28</day>
        <month>12</month>
        <year>2018</year>
      </pub-date>
      <volume>24</volume>
      <issue>12</issue>
      <fpage>1776</fpage>
      <lpage>1799</lpage>
      <uri content-type="arpha" xlink:href="http://openbiodiv.net/6B65CCA0-19D2-5F02-B2C7-50B00651EF36">6B65CCA0-19D2-5F02-B2C7-50B00651EF36</uri>
      <uri content-type="zenodo_dep_id" xlink:href="https://zenodo.org/record/5505911">5505911</uri>
      <history>
        <date date-type="received">
          <day>24</day>
          <month>01</month>
          <year>2018</year>
        </date>
        <date date-type="accepted">
          <day>15</day>
          <month>11</month>
          <year>2018</year>
        </date>
      </history>
      <permissions>
        <copyright-statement>J. Kokila, N. Ramasubramanian, Ravindra Thamma</copyright-statement>
        <license license-type="creative-commons-attribution" xlink:href="" xlink:type="simple">
          <license-p>This article is freely available under the J.UCS Open Content License.</license-p>
        </license>
      </permissions>
      <abstract>
        <label>Abstract</label>
        <p>Recent processors are shrinking in size due to the advancement of technology. Reliability is an important design parameter along with power, cost, and performance. The processors need to be fault tolerant to counter reliability challenges. This work proposes a dynamic thermal and voltage management (DTVM) system which ensures a reasonable level of fault tolerance. The fault tolerance system (FTS) identifies and subsequently can forecast temporary failures at run-time. The temporary failures are dynamically estimated on SoC FPGAs for a class of heterogeneous applications. The dynamic priority scheduling based on absolute deadline is adopted to improve the nature of FTS. Experimental results indicate that the failure rate reduces by 7.2% with the variation of 2% and 12% in temperature and voltage respectively.</p>
      </abstract>
    </article-meta>
  </front>
</article>
