The expanding application of computing systems and the continuing advances in semiconductor technology are forcing the on-chip inclusion of design for dependability features (concurrent fault tolerance). These features detect, log and provide recovery from errors induced by faults concurrently with the operation of the system. A very difficult task is the hardware validation of concurrent fault tolerant design features in a nondestructive, unobtrusive manner. A semi-automated facility has been developed at the University of South Florida for this purpose using Laser Fault Injection (LFI) to simulate soft errors during system operation. The facility provides means to extract target coordinates from the CAD database, synchronize the laser pulse with the operation of and capture health warnings issued by the system under test. The key fault tolerant features (automatic instruction retry on single soft errors) of a state of the art fault tolerant computer for space applications were validated at this facility.