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  <front>
    <journal-meta>
      <journal-id journal-id-type="publisher-id">109</journal-id>
      <journal-id journal-id-type="index">urn:lsid:arphahub.com:pub:3dc5f44e-8666-58db-bc76-a455210e8891</journal-id>
      <journal-title-group>
        <journal-title xml:lang="en">JUCS - Journal of Universal Computer Science</journal-title>
        <abbrev-journal-title xml:lang="en">jucs</abbrev-journal-title>
      </journal-title-group>
      <issn pub-type="ppub">0948-695X</issn>
      <issn pub-type="epub">0948-6968</issn>
      <publisher>
        <publisher-name>Journal of Universal Computer Science</publisher-name>
      </publisher>
    </journal-meta>
    <article-meta>
      <article-id pub-id-type="doi">10.3217/jucs-010-12-1597</article-id>
      <article-id pub-id-type="publisher-id">28324</article-id>
      <article-categories>
        <subj-group subj-group-type="heading">
          <subject>Research Article</subject>
        </subj-group>
        <subj-group subj-group-type="scientific_subject">
          <subject>B.6.2 - Reliability and Testing</subject>
          <subject>F.4.m - Miscellaneous</subject>
          <subject>I.2.6 - Learning</subject>
          <subject>I.2.8 - Problem Solving</subject>
          <subject> Control Methods</subject>
          <subject> and Search</subject>
        </subj-group>
      </article-categories>
      <title-group>
        <article-title>Using Global Structural Relationships of Signals to Accelerate SAT-based Combinational Equivalence Checking</article-title>
      </title-group>
      <contrib-group content-type="authors">
        <contrib contrib-type="author" corresp="yes">
          <name name-style="western">
            <surname>Arora</surname>
            <given-names>Rajat</given-names>
          </name>
          <email xlink:type="simple">raarora@cadence.com</email>
          <xref ref-type="aff" rid="A1">1</xref>
        </contrib>
        <contrib contrib-type="author" corresp="no">
          <name name-style="western">
            <surname>Hsiao</surname>
            <given-names>Michael S.</given-names>
          </name>
          <xref ref-type="aff" rid="A2">2</xref>
        </contrib>
      </contrib-group>
      <aff id="A1">
        <label>1</label>
        <addr-line content-type="verbatim">Cadence Design Systems, San Jose, CA, United States of America</addr-line>
        <institution>Cadence Design Systems</institution>
        <addr-line content-type="city">San Jose, CA</addr-line>
        <country>United States of America</country>
      </aff>
      <aff id="A2">
        <label>2</label>
        <addr-line content-type="verbatim">Department of Electrical &amp; Computer Engineering, Virginia Tech, Blacksburg, VA, United States of America</addr-line>
        <institution>Department of Electrical &amp; Computer Engineering, Virginia Tech</institution>
        <addr-line content-type="city">Blacksburg, VA</addr-line>
        <country>United States of America</country>
      </aff>
      <author-notes>
        <fn fn-type="corresp">
          <p>Corresponding author: Rajat Arora (<email xlink:type="simple">raarora@cadence.com</email>).</p>
        </fn>
        <fn fn-type="edited-by">
          <p>Academic editor: </p>
        </fn>
      </author-notes>
      <pub-date pub-type="collection">
        <year>2004</year>
      </pub-date>
      <pub-date pub-type="epub">
        <day>28</day>
        <month>12</month>
        <year>2004</year>
      </pub-date>
      <volume>10</volume>
      <issue>12</issue>
      <fpage>1597</fpage>
      <lpage>1628</lpage>
      <uri content-type="arpha" xlink:href="http://openbiodiv.net/C78B2411-0C23-5217-8ABB-DFF38D15EA3F">C78B2411-0C23-5217-8ABB-DFF38D15EA3F</uri>
      <uri content-type="zenodo_dep_id" xlink:href="https://zenodo.org/record/6996663">6996663</uri>
      <permissions>
        <copyright-statement>Rajat Arora, Michael S. Hsiao</copyright-statement>
        <license license-type="creative-commons-attribution" xlink:href="" xlink:type="simple">
          <license-p>This article is freely available under the J.UCS Open Content License.</license-p>
        </license>
      </permissions>
      <abstract>
        <label>Abstract</label>
        <p>We propose a novel technique to improve SAT-based Combinational Equivalence Checking (CEC). The idea is to perform a low-cost preprocessing that will statically induce global signal relationships into the original CNF formula of the miter circuit under verification, and hence reduce the complexity of the SAT instance. This efficient and effective preprocessing quickly builds up the implication graph for the miter circuit under verification, yielding a large set of direct, indirect and extended backward implications. These two-node implications spanning the entire circuit are converted into binary clauses, and they are added to the miter CNF formula. The added clauses constrain the search space of the SAT solver and provide correlation among the different variables, which enhances the Boolean Constraint Propagation (BCP). Experimental results on large and difficult ISCAS'85, ISC AS'89 (full scan) and ITC'99 (full scan) CEC instances show that our approach is independent of the state-of-the-art SAT solver used, and that the added clauses help to achieve not eworthy speedup for each of the cases. Also, comparison with Hyper-Resolution (Hypre), Non-Increasing Variable Elimination Resolution (NIVER) and the propositional formula checker HeerHugo, suggests that our technique is more powerful, yielding non-trivial clauses that significantly simplify the SAT instance complexity.</p>
      </abstract>
    </article-meta>
  </front>
</article>
