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  <front>
    <journal-meta>
      <journal-id journal-id-type="publisher-id">109</journal-id>
      <journal-id journal-id-type="index">urn:lsid:arphahub.com:pub:3dc5f44e-8666-58db-bc76-a455210e8891</journal-id>
      <journal-title-group>
        <journal-title xml:lang="en">JUCS - Journal of Universal Computer Science</journal-title>
        <abbrev-journal-title xml:lang="en">jucs</abbrev-journal-title>
      </journal-title-group>
      <issn pub-type="ppub">0948-695X</issn>
      <issn pub-type="epub">0948-6968</issn>
      <publisher>
        <publisher-name>Journal of Universal Computer Science</publisher-name>
      </publisher>
    </journal-meta>
    <article-meta>
      <article-id pub-id-type="doi">10.3217/jucs-014-10-1678</article-id>
      <article-id pub-id-type="publisher-id">29084</article-id>
      <article-categories>
        <subj-group subj-group-type="heading">
          <subject>Research Article</subject>
        </subj-group>
        <subj-group subj-group-type="scientific_subject">
          <subject>B.6.3 - Design Aids</subject>
          <subject>B.7.1 - Types and Design Styles</subject>
          <subject>C.1.3 - Other Architecture Styles</subject>
          <subject>I.2.3 - Deduction and Theorem Proving</subject>
        </subj-group>
      </article-categories>
      <title-group>
        <article-title>An IP Core and GUI for Implementing Multilayer Perceptron with a Fuzzy Activation Function on Configurable Logic Devices</article-title>
      </title-group>
      <contrib-group content-type="authors">
        <contrib contrib-type="author" corresp="yes">
          <name name-style="western">
            <surname>Rosado-Muñoz</surname>
            <given-names>Alfredo</given-names>
          </name>
          <email xlink:type="simple">rosado@uv.es</email>
          <xref ref-type="aff" rid="A1">1</xref>
        </contrib>
        <contrib contrib-type="author" corresp="no">
          <name name-style="western">
            <surname>Gomez-Chova</surname>
            <given-names>Luis</given-names>
          </name>
          <xref ref-type="aff" rid="A1">1</xref>
        </contrib>
        <contrib contrib-type="author" corresp="no">
          <name name-style="western">
            <surname>Francés</surname>
            <given-names>Joan Vila</given-names>
          </name>
          <xref ref-type="aff" rid="A1">1</xref>
        </contrib>
      </contrib-group>
      <aff id="A1">
        <label>1</label>
        <addr-line content-type="verbatim">University of Valencia, Valencia, Spain</addr-line>
        <institution>University of Valencia</institution>
        <addr-line content-type="city">Valencia</addr-line>
        <country>Spain</country>
      </aff>
      <author-notes>
        <fn fn-type="corresp">
          <p>Corresponding author: Alfredo Rosado-Muñoz (<email xlink:type="simple">rosado@uv.es</email>).</p>
        </fn>
        <fn fn-type="edited-by">
          <p>Academic editor: </p>
        </fn>
      </author-notes>
      <pub-date pub-type="collection">
        <year>2008</year>
      </pub-date>
      <pub-date pub-type="epub">
        <day>28</day>
        <month>05</month>
        <year>2008</year>
      </pub-date>
      <volume>14</volume>
      <issue>10</issue>
      <fpage>1678</fpage>
      <lpage>1694</lpage>
      <uri content-type="arpha" xlink:href="http://openbiodiv.net/B24EF697-6C4E-5599-B2C8-99A98EFD01FA">B24EF697-6C4E-5599-B2C8-99A98EFD01FA</uri>
      <uri content-type="zenodo_dep_id" xlink:href="https://zenodo.org/record/7000304">7000304</uri>
      <permissions>
        <copyright-statement>Alfredo Rosado-Muñoz, Luis Gomez-Chova, Joan Vila Francés</copyright-statement>
        <license license-type="creative-commons-attribution" xlink:href="" xlink:type="simple">
          <license-p>This article is freely available under the J.UCS Open Content License.</license-p>
        </license>
      </permissions>
      <abstract>
        <label>Abstract</label>
        <p>This paper describes the development of an Intellectual Property (IP) core in VHDL able to implement a Multilayer Perceptron (MLP) artificial neural network (ANN) topology with up to 2 hidden layers, 128 neurons, and 31 inputs per neuron. Neural network models are usually developed by using programming languages, such as Matlab®. However, their implementation in configurable logic hardware requires the use of some other tools and hardware description languages, such as as VHDL. For easy migration, a Matlab Graphical User Interface (GUI) to automatically translate the ANN architecture to VHDL code has been developed. In addition, the use of an activation function based on fuzzy logic for the implementation of the MLP neural network simplifies the logic and improves the results. The environment was tested using a typical prediction problem, the Mackey-Glass series, where several ANN topologies were generated, tested and implemented in an FPGA. Results show the excellent agreement between the results provided by the software model and the hardware implementation.</p>
      </abstract>
    </article-meta>
  </front>
</article>
