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JUCS - Journal of Universal Computer Science 28(10): 1030-1057
https://doi.org/10.3897/jucs.86282 (28 Oct 2022)
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JUCS - Journal of Universal Computer Science 28(10): 1030-1057
doi: 10.3897/jucs.86282
Received: 08 May 2022 | Approved: 30 Aug 2022 | Published: 28 Oct 2022
This article is part of:
JUCS - Journal of Universal Computer Science 28(10)
Authors
   
Abd Al-Rahman Al-Nounou
Jordan University of Science and Technology, Irbid, Jordan
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Osama Al-Khaleel - Corresponding author
Jordan University of Science and Technology, Irbid, Jordan
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Fadi Obeidat
Cadence Design Systems, Austin, United States of America
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Mohammad Al-Khaleel
Khalifa University, Abu Dhabi, United Arab Emirates
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Author contributions
We present a methodology for designing binary multipliers where different sizes customized partial products generation (CPPG) cells are designed and used as smaller building blocks. The sizes of the designed CPPG cells are 2×2, 3×3, 4×4, 5×5, and 6×6. We use these cells to build 8×8, 16×16, 32×32, 64×64, and 128×128 binary multipliers. All of the CPPG cells and the binary multipliers are described using the VHDL language, tested, and implemented using XILINX ISE 14.6 tools targeting different FPGA families.
Conflict of interest
The authors have declared that no competing interests exist.
Supporting agencies
JUST-Deanship of Research
This is an open access article distributed under the terms of the Creative Commons Attribution License (CC BY-ND 4.0). This license allows reusers to copy and distribute the material in any medium or format in unadapted form only, and only so long as attribution is given to the creator. The license allows for commercial use.
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