JUCS - Journal of Universal Computer Science 24(12): 1776-1799, doi: 10.3217/jucs-024-12-1776
Dynamic Estimation of Temporary Failure in SoC FPGAs for Heterogeneous Applications
J. Kokila‡, N. Ramasubramanian‡, Ravindra Thamma§‡ National Institute of Technology, Tiruchirappalli, India§ Central Connecticut State University, New Britain, United States of America
Corresponding author: J. Kokila ( 406114002@nitt.edu ) © J. Kokila, N. Ramasubramanian, Ravindra Thamma. This article is freely available under the J.UCS Open Content License. Citation:
Kokila J, Ramasubramanian N, Thamma R (2018) Dynamic Estimation of Temporary Failure in SoC FPGAs for Heterogeneous Applications. JUCS - Journal of Universal Computer Science 24(12): 1776-1799. https://doi.org/10.3217/jucs-024-12-1776 |  |
Abstract
Recent processors are shrinking in size due to the advancement of technology. Reliability is an important design parameter along with power, cost, and performance. The processors need to be fault tolerant to counter reliability challenges. This work proposes a dynamic thermal and voltage management (DTVM) system which ensures a reasonable level of fault tolerance. The fault tolerance system (FTS) identifies and subsequently can forecast temporary failures at run-time. The temporary failures are dynamically estimated on SoC FPGAs for a class of heterogeneous applications. The dynamic priority scheduling based on absolute deadline is adopted to improve the nature of FTS. Experimental results indicate that the failure rate reduces by 7.2% with the variation of 2% and 12% in temperature and voltage respectively.
Keywords
fault tolerance system, system on chip design, priority dynamic scheduling algorithm, physics of failure, modified voltage lifetime model