JUCS - Journal of Universal Computer Science 1(11): 728-743, doi: 10.3217/jucs-001-11-0728
Testing a High-Speed Data Path The Design of the RSAb Crypto Chip
expand article infoWolfgang Mayerwieser‡, Karl C. Posch‡, Reinhard Posch§, Volker Schindler‡
‡ IAIK, Graz University of Technology, Austria§ Institute for Applied Information Processing and Communications, Graz University of Technology, Graz, Austria

Corresponding author: Wolfgang Mayerwieser ( wmayer@iaik.tu-graz.ac.at )

© Wolfgang Mayerwieser, Karl Posch, Reinhard Posch, Volker Schindler.
This article is freely available under the J.UCS Open Content License.
Citation: Mayerwieser W, Posch KC, Posch R, Schindler V (1995) Testing a High-Speed Data Path The Design of the RSAb Crypto Chip. JUCS - Journal of Universal Computer Science 1(11): 728-743. https://doi.org/10.3217/jucs-001-11-0728
Open Access
Abstract
High speed devices for public key cryptography are of emerging interest. For this reason, the crypto chip was designed. It is an architecture capable of performing fast RSA encryption and other cryptographic algorithms based on modulo multiplication. Besides the modulo multiplication algorithm called FastMM, the reasons for its high computation speed are the As Parallel As Possible (APAP) architecture, as well as the high operation frequency. The crypto chip also contains on-chip RAM and a special-purpose control logic, enabling special features like encrypted key loading. However, this control mechanism influences to some extend testability of the MM data path which is the heart of the chip. For this reason, the crypto chip has been designed to be able to evaluate the behaviour of the pure MM data path. In the following, we describe the strategies used with the crypto chip for testing the MM data path under realistical conditions. In this context, analyzing control signal flow turns out to be the key action.This work has been sponsored as part of the project Nr. P9384PHY "Sichere Kommunikation bei hohen Geschwindigkeiten" by the Austrian Science Foundation.
Keywords
high speed multipliers, hardware algorithms, design for testability, public key cryptography