JUCS - Journal of Universal Computer Science 5(11): 765-776, doi: 10.3217/jucs-005-11-0765
Matrix Method to Detect Logic Hazards in Combinational Circuits with EX-OR Gates
expand article infoE. C. Tan‡, M. H. Ho‡
‡ Nanyang Technological University, Singapore

Corresponding author: E. Tan ( asectan@ntu.edu.sg )

© E. Tan, M. Ho.
This article is freely available under the J.UCS Open Content License.
Citation: Tan EC, Ho MH (1999) Matrix Method to Detect Logic Hazards in Combinational Circuits with EX-OR Gates. JUCS - Journal of Universal Computer Science 5(11): 765-776. https://doi.org/10.3217/jucs-005-11-0765
Open Access
Abstract
A matrix method is extended to include the detection of logic hazards in combinational logic circuits involving EX-OR gates. Essentially, the method generates 0- and 1-sets, or P- and S-sets, of all nodes in each gate level of a circuit progressively until it reaches the output of the circuit. The sets generated are subsequently used to determine the existence of static or dynamic hazards.
Keywords
hardware, logic hazards, exclusive-OR gates, matrix method