A Dynamically and Partially Reconfigurable Implementation of the IDEA Algorithm Using FPGAs and Handel-C

José Granado-Criado; Miguel A. Vega-Rodríguez; Juan Sánchez-Pérez; Juan Gómez-Pulido

doi:10.3217/jucs-013-03-0407

JUCS - Journal of Universal Computer Science 13(3): 407-418, doi: 10.3217/jucs-013-03-0407

A Dynamically and Partially Reconfigurable Implementation of the IDEA Algorithm Using FPGAs and Handel-C

José M. Granado-Criado^‡, Miguel A. Vega-Rodríguez, Juan M. Sánchez-Pérez^‡, Juan A. Gómez-Pulido^§

‡ University of Extremadura, Cáceres, Spain§ Universidad de Extremadura, Cáceres, Spain

Corresponding author: José Granado-Criado ( granado@unex.es )

This article is freely available under the J.UCS Open Content License.

Citation: Granado-Criado JM, Vega-Rodríguez MA, Sánchez-Pérez JM, Gómez-Pulido JA (2007) A Dynamically and Partially Reconfigurable Implementation of the IDEA Algorithm Using FPGAs and Handel-C. JUCS - Journal of Universal Computer Science 13(3): 407-418. https://doi.org/10.3217/jucs-013-03-0407

Abstract

Nowadays, the information security has achieved a great importance, both when information is sent through a non-secure network (as the Internet) and when data are stored in massive storage devices. The cryptographic algorithms are used in order to guarantee the security of data sent or stored. A lot of research is being done in order to improve the performance of the current cryptographic algorithms, including the use of FPGAs. In this work we present an implementation of the IDEA cryptographic algorithm using reconfigurable hardware (FPGAs). In addition, in order to improve the performance of the algorithm, partial and dynamic reconfiguration has been used to implement our final circuit. This fact allows us to obtain a very high encryption speed (14.757 Gb/s), getting better results than those found in the literature.

Keywords

FPGA, partial and dynamic reconfiguration, IDEA, cryptography