DOI: 10.3897/jucs.175236

Authors: Christian Schlager, Atif Mashkoor

Abstract: The automotive industry increasingly relies on complex embedded systems that inte-grate software, electronic hardware, electromechanical, and mechanical components. To ensure quality, the Automotive Software Process Improvement and Capability Determination (ASPICE) framework has been extended by cybersecurity, which has become a critical concern. Recognizing these risks, the United Nations Economic Commission for Europe (UNECE) introduced Regulation No. 155 in 2021, establishing mandatory provisions for vehicle type approval and cybersecurity management. To address these regulatory demands, ASPICE for Cybersecurity extends the standard ASPICE model with additional processes focused on identifying, analyzing, and mitigating security threats. While the combined assessment of ASPICE and ASPICE for Cybersecurity ensures both process maturity and security compliance, it presents significant challenges for organizations. Conducting separate assessments for ASPICE and ASPICE for Cybersecurity increases time, cost, and organizational workload, as many process areas overlap in scope and evidence. This paper proposes a unified assessment approach designed to evaluate compliance with both ASPICE and ASPICE for Cybersecurity in a single, integrated process. The approach involves systematically mapping equivalent or related process areas across the two models. This approach was applied in an industry case study, demonstrating a reduction in total assessment time and minimizing disruption to development teams. The results indicate that integrated assessments can maintain the rigor and comprehensiveness of separate evaluations while improving efficiency and reducing operational burden.

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DOI: 10.3897/jucs.154482

Authors: Dimitrios Psilias, Athanasios Milidonis, Ioannis Voyiatzis

Abstract: This work presents a novel Field Programmable Gate Array (FPGA)-based architecture for encrypting telemetry together with high-definition video data in unmanned aerial vehicles (UAVs). The design uses the Advanced Encryption Standard (AES-128) to secure data and video streams, ensuring protection against cyberattacks. The proposed system integrates a pipeline data path for video and telemetry data, coupled with FIFO buffers, enabling efficient handling of different bandwidth requirements while maintaining high throughput. Our platform encrypts/decrypts both down-stream and up-stream telemetry data and encrypts down-stream of video data. To the best of our knowledge, no such architecture has been proposed in the literature, as existing research focus on encrypting only a part of the aforementioned types of data. Experimental results demonstrate that the proposed architecture performs efficiently without adding serious execution delays comparing to existing FPGA platforms, while keeping energy consumption low.

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DOI: 10.3897/jucs.120840

Authors: Soraya Setti Ahmed, Yahya Slimani, Riadh Frefita

Abstract: Fault tolerance approaches in distributed systems are essentially based on replication and checkpointing. Each of these approaches has its advantages and limitations. This paper has two objectives: first, it proposes a fault tolerance approach based on the nodes status of a distributed system. For this purpose, it defines 3 nodes status: safety, faulty and potentially faulty. With respect of classical node status (safety, faulty), it introduces a new status that we call potentially faulty. This last node allows to enhance the availability of a distributed system. Second, it discusses the efficiency of the proposed model on two types of architectures: virtual multi-node cluster and a physical multi-node cluster with WIFI connection. Experiments have showed that proposed approach increases the system performance throughput and its fault tolerance level.

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DOI: 10.3897/jucs.112790

Authors: Florian Skopik, Arndt Bonitz, Daniel Slamanig, Markus Kirschner, Wolfgang Hacker

Abstract: Military field operations place high demands on information and communication technology (ICT) devices, both in terms of reliability and security. These requirements include robustness against environmental influences such as vibrations, water, and humidity as well as protection against physical attacks and cyber-attacks. Attempts to compromise a device must be detected immediately, and if necessary, trigger automated countermeasures such as alarms, partial deactivation or emergency wiping of all data. In this work, we specifically focus on cyber security issues and aim to deliver a concept for a device that can be used in multiple security domains, isolating mission-specific data from each other without the risk of data spillover. For that purpose, we outline a high-level concept for a resilient single device concept that is able to withstand common intrusion attempts. We identify threat agents, misuse cases and the risks of a single device concept for multiple security domains and evaluate the most pressing issues. Based on the identified risks, we determine additional mitigation measures and discuss their applicability. We foresee our work to provide valuable insights into the requirements on and design decisions of highly secure mobile device solutions.

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DOI: 10.3897/jucs.112797

Authors: Lorenz Gillner, Ekaterina Auer

Abstract: In this paper, we describe the requirements for traceable open-source data retrieval in the context of computation of BRCA1/2 mutation probabilities (mutations in two tumor-suppressor genes responsible for hereditary BReast or/and ovarian CAncer). We show how such data can be used to develop a Dempster-Shafer model for computing the probability of BRCA1/2 mutations enhanced by taking into account the actual age of a patient or a family member in an appropriate way even if it is not known exactly. The model is compared with PENN II and BOADICEA (based on undisclosed data), two established platforms for this purpose accessible online, as well as with our own previous models. A proof-of-concept implementation shows that set-based techniques are able to provide better information about mutation probabilities, simultaneously highlighting the necessity for ground truth data of high quality.

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DOI: 10.3897/jucs.86282

Authors: Abd Al-Rahman Al-Nounou, Osama Al-Khaleel, Fadi Obeidat, Mohammad Al-Khaleel

Abstract: Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes customized partial products generation (CPPG) cells are designed and used as smaller building blocks. The sizes of the designed CPPG cells are 2×2, 3×3, 4×4, 5×5, and 6×6. We use these cells to build 8×8, 16×16, 32×32, 64×64, and 128×128 binary multipliers. All of the CPPG cells and the binary multipliers are described using the VHDL language, tested, and implemented using XILINX ISE 14.6 tools targeting different FPGA families. The implementation results show that the best performance is achieved when cell 3×3 is used and Virtex-7 FPGA is targeted. The binary multipliers that are designed using the proposed CPPG cells achieve better performance when compared with the binary multipliers presented in the literature. As an application that utilizes the proposed multiplier, a Multiply-Accumulate (MAC) unit is designed and implemented in Spartan-3E. The implementation results of the MAC unit demonstrate the effectiveness of the proposed multiplier.

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DOI: 10.3897/jucs.77247

Authors: Christopher Cichiwskyj, Gregor Schiele

Abstract: When the complexity of a problem rises, its solution requires more hardware resources. A usual way to solve this is to use larger processors and add more memory. When using Field Programmable Gate-Arrays (FPGAs), which can instantiate arbitrary circuit designs, a larger, more costly and power hungry chip is used. In this paper we propose a different approach, namely to split the problem into a graph of interdependent smaller tasks and to reconfigure a small FPGA during runtime to execute each of these tasks efficiently sequentially. This can result in cheaper and more energy efficient systems that can execute very complex problems locally. We present a basic analytical model, evaluate its accuracy and discuss initial insight from it.

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DOI: 10.3897/jucs.71831

Authors: Nermin Kajtazovic, Peter Hödl, Leo Happ Botler

Abstract: Coexistence of software components and functions of different criticality in a single computing platform has challenged the safety community for the past two decades. Despite efforts that have been made so far, dealing with mixed-criticality has still left some room for improvements. One particular concern here is that partitioning of hardware and software resources with regard to criticality (safety related, non-safety related) has direct implications on how safety measures need to be realised. For example, a self-test that must meet certain diagnostic coverage for the microcontroller core by inspecting its instructions, needs to cover only those instructions which are able to affect a safety function. Available software mechanisms and tools are to a certain extent still unable to deal with such a fine-grained selection of resources. In this work, we introduce a compiler extension and language support which enable accurate selection of data based on their criticality. The compiler extension serves to establish detailed traceability between the software code and its representation in runtime memory. With the language support, the individual data elements can be classified based on the desired safety integrity level. As a result, safety measures that operate on data (e.g. Abraham test for SRAM can achieve better coverage. The method has been evaluated and applied to industrial safety controllers. We provide here relevant performance figures and discuss possible applications of the method in other fields.

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DOI: 10.3897/jucs.69617

Authors: Edinelço Dalcumune, Luis Antonio Brasil Kowada, André da Cunha Ribeiro, Celina Miraglia Herrera de Figueiredo, Franklin de Lima Marquezino

Abstract: We present a new algorithm for synthesis of reversible circuits for arbitrary n-bit bijective functions. This algorithm uses generalized Toffoli gates, which include positive and negative controls. Our algorithm is divided into two parts. First, we use partially controlled gen- eralized Toffoli gates, progressively increasing the number of controls. Second, exploring the properties of the representation of permutations in disjoint cycles, we apply generalized Toffoli gates with controls on all lines except for the target line. Therefore, new in the method is the fact that the obtained circuits use first low cost gates and consider increasing costs towards the end of the synthesis. In addition, we employ two bidirectional synthesis strategies to improve the gate count, which is the metric used to compare the results obtained by our algorithm with the results presented in the literature. Accordingly, our experimental results consider all 3-bit bijective functions and twenty widely used benchmark functions. The results obtained by our synthesis algorithm are competitive when compared with the best results known in the literature, considering as a complexity metric just the number of gates, as done by alternative best heuristics found in the literature. For example, for all 3-bit bijective functions using generalized Toffoli gates library, we obtained the best so far average count of 5.23.

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DOI: 10.3897/jucs.65094

Authors: Yadira Quiñonez, Carmen Lizarraga, Raquel Aguayo, David Arredondo

Abstract: Technology is currently a significant benchmark in any application area; science and technology have permitted the invention of tools and devices that simplify daily activities by developing software engineering applications that provide automated solutions. In this sense, this work proposes two architectures that allow communication between the electronic device and the mobile application remotely, using the GSM/GPRS communication services and the Twitter social network. This development aims to control dogs' feeding adequately and healthily, providing the ration of food a dog needs according to the daily energy requirements. A nutritional assessment has also been performed considering different factors such as the size, breed, and weight of the dog to calculate the daily ration of healthy and balanced food according to daily energy requirements. Essentially, the electronic device consists of two parts: on the one hand, the electronic design is formed with an Arduino board, a Sim900 module to send and receive text messages, and the ESP8266 Wi-Fi serial transceiver module, which allows establishing the internet connection to receive the tweet that users post, both modules permit remote communication with the device using the Arduino board. On the other hand, the mobile application developed on Android uses a standard design according to the Google material design guidelines, allowing the owner to feed, schedule the feeding, review the dog's food history, and receive alerts when the food is going to be finished.

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DOI: 10.3897/jucs.2020.079

Authors: Ján Molnár, Simona Kirešová, Tibor Vince, Dobroslav Kováč, Patrik Jacko, Matej Bereš, Peter Hrabovský

Abstract: IoT technology is gaining more and more popularity in practice, as it collects, processes, evaluates and stores important measured data. The IoT is used every day in the work, in the home or smart houses or in public areas. It realizes the connectivity between real world and digital world which means, that it converts physical quantities of the real world in the form of analog signals into digital numbers stored in clauds. It is essential that students gain practical experience in the design and implementation of the IoT systems during their studies. The article first describes IoT issues and communication protocols used in IoT generally are closer described. Then the design and implementation of an educational model of IoT system - Weather station with the ThingSpeak cloud support is described. The created IoT model interconnects microcontroller programming, sensors and measuring, cloud API interfaces, MATLAB scripts which are useful to analyses the stored data, Windows and Android application developing.

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DOI: 10.3897/jucs.2020.074

Authors: Tibor Vince, Matej Bereš, Irena Kováčová, Ján Molnár, Branislav Fecko, Jozef Dziak, Iveta Tomčiková, Milan Guzan

Abstract: The paper presents analyses of the implementation of IoT in the patent technology of the remote measuring laboratory (VMLab). The technology allows to create a new electrical connection between different devices, where the connection diagram was not defined before. This may be done remotely around the world. To begin with, an application of this technology as a remote measuring laboratory is presented and described. Analyses of the possible application of IoT technology in the Remote Measurement Laboratory (VMLAB) with a final design are also presented. The research focuses on an efficient way to retrieve measured values synchronized over the Internet from multiple measuring devices and controllable devices, without an Ethernet or Wi-Fi interface from the manufacturer. The analyses may also be useful when implementing an additional IoT approach to existing systems.

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DOI: 10.3217/jucs-025-11-1396

Authors: Steffen Wendzel, Florian Link, Daniela Eller, Wojciech Mazurczyk

Abstract: Network covert channels enable stealthy communications for malware and data exfiltration. For this reason, developing effective countermeasures for these threats is important for the protection of individuals and organizations. However, due to the large number of available covert channel techniques, it is considered impractical to develop countermeasures for all existing covert channels. In recent years, researchers started to develop countermeasures that (instead of only countering one particular hiding technique) can be applied to a whole family of similar hiding techniques. These families are referred to as hiding patterns. Considering above, the main contribution of this paper is to introduce the concept of countermeasure variation. Countermeasure variation is a slight modification of a given countermeasure that was designed to detect covert channels of one specific hiding pattern so that the countermeasure can also detect covert channels that are representing other hiding patterns. We exemplify countermeasure variation using the compressibility score, the ε-similarity and the regularity metric originally presented by Cabuk et al. All three methods are used to detect covert channels that utilize the Inter-packet Times pattern and we show that countermeasure variation allows the application of these countermeasures to detect covert channels of the Size Modulation pattern, too.

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DOI: 10.3217/jucs-025-09-1199

Authors: François Bouchaud, Gilles Grimaud, Thomas Vantroys, Pierrick Buret

Abstract: The Internet of Things (IoT) is everywhere around us. Smart communicating objects are offering the digitalization of lives. They create new opportunities within criminal investigations. In recent years, the scientific community sought to develop a common digital framework and methodology adapted to IoT-based infrastructure. However, the difficulty in exploiting the IoT lies in the heterogeneous nature of the devices, the lack of standards and the complex architecture. Although digital forensics are considered and adopted in IoT investigations, this work only focuses on the collection. The identification phase is quite unexplored. It addresses the challenges of locating hidden devices and finding the best evidence to be collected. The matter of facts is the traditional method of digital forensics does not fully fit the IoT environment. Furthermore, the investigator can no longer consider a connected object as a single device, but as an interconnected whole one, anchored in a cross-disciplinary environment. This paper presents the methodology for identifying and classifying connected objects in search of the best evidence to be collected. It offers techniques for detecting and locating the appropriate equipment. Based on frequency mapping and interactions, it transfers the concept of "fingerprinting" into the field of crime scene. It focuses on the technical and data criteria to successfully select the relevant IoT devices. It gives a general classiffication as well as the limits of such an approach. It shows the collection of digital evidence by focusing on pertinent information from the Internet of Things.

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DOI: 10.3217/jucs-024-12-1776

Authors: J. Kokila, N. Ramasubramanian, Ravindra Thamma

Abstract: Recent processors are shrinking in size due to the advancement of technology. Reliability is an important design parameter along with power, cost, and performance. The processors need to be fault tolerant to counter reliability challenges. This work proposes a dynamic thermal and voltage management (DTVM) system which ensures a reasonable level of fault tolerance. The fault tolerance system (FTS) identifies and subsequently can forecast temporary failures at run-time. The temporary failures are dynamically estimated on SoC FPGAs for a class of heterogeneous applications. The dynamic priority scheduling based on absolute deadline is adopted to improve the nature of FTS. Experimental results indicate that the failure rate reduces by 7.2% with the variation of 2% and 12% in temperature and voltage respectively.

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DOI: 10.3217/jucs-024-12-1758

Authors: Darwin Alulema, Javier Criado, Luis Iribarne

Abstract: The Internet of Things has presented a rapid development, due to the over-crowding of hardware and software platforms, greater deployment of communications networks, development of data analysis tools, among others. This development has led to a boom in applications focused on areas as varied as Smart Cities, Smart Agro, Smart Buildings, Smart Home, and Smart Health, in which people and things are interconnected. This is one of the reasons by which a review of the main technologies involved in the emergence of the Internet of Things must be carried out to determine those characteristics allowing that interconnection, but without neglecting security. This issue allows the user to feel con dent to use these new services. In this work, we propose a cross-device architecture that integrates technologies and implementations in homes, and uses basic authentication as a security scheme. To validate the cross-device proposal, a case study scenario has been designed, including and integrating digital-TV (DTV), Smart Phones and wearables devices for monitoring users physical activity.

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DOI: 10.3217/jucs-024-09-1217

Authors: Difeng Yu, Hai-Ning Liang, Feiyu Lu, Vijayakumar Nanjappan, Konstantinos Papangelis, Wei Wang

Abstract: Target selection is one of the most common and important tasks in interactive systems. Within virtual reality environments, target selection can pose extra challenges to users because targets can be located far away, clustered together, and occluded from view. Although selection techniques have been explored, it is often unclear which techniques perform better across different environmental target density levels and which have higher levels of usability especially for recently released commercial head-mounted display (HMD) virtual reality systems and input devices. In this paper, we first review previous studies on target selection in HMD VR environments. We then compare the performances of three main techniques or metaphors (RayCasting, Virtual Hand, and Hand-Extension) using recently marketed VR headsets and input devices under different density conditions and selection areas. After, we select the best two techniques (RayCasting and Virtual Hand) for the second experiment to explore their relative performance and usability by adding different feedback to these two techniques. In the third experiment, we implemented three techniques with pointing facilitators and compared them against the best techniques from the second experiment, RayCasting with visual feedback, to assess their performance, error rates, learning effects, and usability. The three studies altogether suggest the best target selection features, based on techniques, feedback, and pointing facilitators for target density conditions in HMD VR environments.

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DOI: 10.3217/jucs-024-04-0515

Authors: Xiang Wang, Weike Wang, Bin Xu, Pei Du, Lin Li, Muyang Liu

Abstract: Embedded systems are subjected to various adversaries including software attacks, physical attacks, and side channel attacks. Most of these malicious attacks can lead to the invalid execution of programs, and launch of destructive actions or reveal critical information. However, most previous security mechanisms suffer from coarse checking granularity and unacceptable performance overhead, due to strict restriction on system resources. This paper presents a fine-grained hardware-based security approach to ensure runtime code integrity in the embedded systems by offline profiling of the program features and runtime integrity check. We design a hardware implemented instruction stream integrity checker (ISIC) to perform runtime checking of pre-extracted features. Any invalid execution of the program will trigger the corresponding exception signal. We implement the ISIC with OR1200 processor on XC5VLX50T field-programmable gate array (FPGA). The experimental results show that the proposed approach can detect all the attacks destructing integrity of the instruction stream, and the performance overhead induced by the security mechanism is less than 3.45% according to the selected benchmarks.

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DOI: 10.3217/jucs-023-06-0560

Authors: Monika Kapus-Kolar

Abstract: In the optimization of test sets for black-box conformance testing of objects specified and modelled as a finite state machine (FSM), a popular transformation is that under a certain precondition, a tail of a test is removed and appended to some other test. We propose a weaker precondition under which the transformation remains fault-coverage-preserving. Along with a weaker precondition, we propose some weaker sufficient conditions for its satisfaction. To demonstrate the usefulness of the relaxations, we employ them for generalizing the checking sequence (CS) construction method of Inan and Ural (1999), to incomplete FSMs and with additional dimensions for CS optimization. The method and its generalized version are exceptional in that they can handle also the case where the upper bound, call it m, assumed for the size of the state set of the FSM under test is not less than twice the size, call it n, of the state set of the specification FSM. We prove that for complete FSMs, the additional optimization dimensions facilitate that in the limit for increasingly large (m/n) and (a/m), with a the number of the defined inputs, the factor of CS length reduction is of the order

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DOI: 10.3217/jucs-022-11-1437

Authors: Vladimir Ciric, Aleksandar Cvetkovic, Ivan Milentijevic, Oliver Vojinovic

Abstract: Motivated by the large number of vertices that future technologies will put in the front of path-search algorithms, and inspired by highly regular 2D mesh structures that exist in the domain applications, in this paper we propose a new allpairs shortest paths algorithm, for any given regular 2D mesh topology, with complexity Ο(|V|2), where |V| is the number of vertices in the graph. The proposed algorithm can achieve better runtime than other known algorithms at the cost of narrowing the scope of the graphs that it can process to the graphs with regular 2D topology. The algorithm is developed into formalism by algebraic transformations in tropical algebra of the well-known Floyd-Warshall's algorithm. First we prove the equivalency of the Floyd-Warshall's algorithm and its tropical algebraic representation, and put the transformations of the algorithm into the algebraic domain. Secondly, having in mind the structure of the target class of graphs, we transform the original algorithm in the algebraic domain and develop a simple, low-complexity iterative algorithm for all-pairs shortest paths calculation. Decreasing of computational complexity can contribute to better exploitation of the algorithm in the wide range of applications from hardware design in new emerging technologies to big data problems in information technologies.

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DOI: 10.3217/jucs-021-11-1454

Authors: Ahmed Al-Zahrani, Hassan Mathkour, Hassan Abdalla

Abstract: Feature-based approaches play an important role and are widely applied in extractive summarization. In this paper, we use particle swarm optimization (PSO) to evaluate the effectiveness of different state-of-the-art features used to summarize Arabic text. The PSO is trained on the Essex Arabic summaries corpus data to determine the best particle that represents the most appropriate simple/combination of eight informative/structure features used regularly by Arab summarizers. Based on the elected features and their relevant weights in each PSO iteration, the input text sentences are scored and ranked to extract the top ranking sentences in the form of an output summary. The output summary is then compared with a reference summary using the cosine similarity function as the fitness function. The experimental results illustrate that Arabs summarize texts simply, focusing on the first sentence of each paragraph.

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DOI: 10.3217/jucs-021-02-0177

Authors: Jose Gutiérrez-Rivas, Simon Holmbacka, Miguel Míndez-Macías, Wictor Lund, Sebastien Lafond, Johan Lilius, Javier Díaz-Alonso

Abstract: Safety-critical systems and certification standards are the bare essential elements for the development process of avionics, automotive and industrial embedded systems. The necessity of including non-safety capabilities to reduce the price of these systems has resulted in a new type of critical systems, the mixed-criticality ones. These systems should be able to execute safety-critical applications but, at the same time, to run non-safety-critical functionalities without affecting the integrity of the safety-critical tasks. This paper presents a new system architecture which includes safety-critical and non-safety-critical parts in order to form a mixed-criticality system. The system consists of a reliable platform with a dual-core processor (implemented using a FPGA) architecture designed as open-hardware, running two isolated real-time operating systems which are connected through a safe core-to-core communication channel that executes the safety-critical applications. Moreover, the safety-critical system is connected to an external processor, an ARM9, which is used as an external sensing system. The ARM9 runs the non-safety-critical applications and allows the system to insert modifications updating without affecting the safety capabilities of the safety-critical part. This platform is described providing evidences of the isolation between safety-critical (SC) and non-safety-critical (NSC) applications, as well as describing an updating methodology for non-safety-critical applications. This system is validated using a complete and reliable application for safe emergency stop applications for industrial machinery.

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DOI: 10.3217/jucs-020-10-1488

Authors: Puyuan Yang, Peiquan Jin, Lihua Yue

Abstract: In recent years, mobile operating systems, represented by android and iOS, have become more and more popular in smartphones. However, the energy issue in smartphones, which refers to the poor battery capacity and management schemes, has been the bottle-neck to further advance the development in this area. Generally, mobile applications have to consider both performance and energy consumption. But unfortunately, few works have been focused on this issue. In this paper, we aim at conducting an experimental study on the performance and energy tradeoffs for mobile applications. In particular, we focus on mobile database applications as they are one of the basic applications on mobile operating systems. In detail, we use the android system as the basic mobile platform, and the TPC-H benchmark as the workload, and build a benchmark platform called TPCdroid to conduct performance and energy measurement. In TPCdroid, we control the mobile database performance by changing the processor frequency. The initial experimental results show that lowering frequency is not always helpful for reducing energy consumption. Moreover, we found that the traditional energy reducing technologies based on X86 and magnetic disks are not suitable for mobile database applications running on ARM and flash memory. Finally, we analyse the relationship between performance and energy consumption under different kinds of workloads, which is done by adjusting the parameters reflecting performance and energy consumption for mobile database applications. The results show that the energy consumption has a dynamic connection with the performance in mobile database applications.

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DOI: 10.3217/jucs-019-16-2368

Authors: Leandro Marin, Antonio Jara, Antonio Skarmeta

Abstract: Cryptographic primitives are the key component in the security protocols to support the authentication, key management and secure communication establishment. For that reason, this work presents the optimization of the Elliptic Curve Cryptography through the usage of Shifting Primes for constrained devices. Specifically, this presents the optimization for the chipsets JN51XX from NXP/Jennic, which are based on OpenRISC architecture and offer a class-2 constrained device. In details, Shifting Primes features have allowed to optimize the multiplication and squaring through a double accumulator and shifting reduction. This work is ancillary to the previous works about optimization of Shifting Primes for class-1 constrained devices. The optimization of the Elliptic Curve Cryptography for the class-2 constrained devices brings several opportunities for realistic scenarios, where the security interoperability between a gateway (class-2 device) and end-nodes (class 1 devices) is a major requirement.

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DOI: 10.3217/jucs-019-15-2292

Authors: Javier Fernández, Juan Augusto, Giuseppe Trombino, Ralf Seepold, Natividad Madrid

Abstract: Traders are required to work in the financial market with highly complex information and to perform efficiently under high levels of psychological pressure. Multiple disciplines, from programs with artificial intelligence to complex mathematical functions, are used to help traders in their effort to maximize profits. However, an essential problem not yet considered in this rapidly evolving environment is that traders are not supported to adequately manage how stress influences their decisions. This paper takes into consideration the negative influences of stress on individuals and proposes a system designed to support traders by providing them with information that can reduce the likelihood of poor decision-making. The system has been designed considering both technical and physiological aspects to make information available in a suitable way. Biometric sensors are used to collect data associated with stress, a software platform then analyses this information and displays it to the trader. The resulting system is capable of making individual traders, as well as teams of traders, self-aware of their levels of stress. The system has been tested in real environments and the results provide evidence that self-aware traders benefit from the system by reducing risky decision-making.

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DOI: 10.3217/jucs-019-09-1242

Authors: Jan Havlik, Lenka Lhotska, Jakub Parak, Jan Dvorak, Zdenek Horcik, Matous Pokorny

Abstract: Remote patient monitoring is gradually attracting more attention as the population in developed countries ages, and as chronic diseases appear more frequently in the population. Miniaturization in electronics and mobile technologies has led to rapid development of various wearable systems for remote monitoring of vital signs, supervision systems in home care, assistive technologies and similar systems. There is a significant demand for developing the necessary devices very rapidly, especially for shortening the way from an idea to a first function sample. This paper presents a solution for rapidly developing devices for telemedical applications, remote monitoring and assistive technologies. The approach used here is to design and realize a modular system consisting of input modules for signal acquisition, a control unit for signal pre-processing, handshaking of data communication, controlling the system and providing the user interface and communication modules for data transmission to a superordinate system. A description of specific applications developed on the basis of the system is also presented in the paper.

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DOI: 10.3217/jucs-019-03-0301

Authors: Enrique Cantó, Mariano Fons, Francesc Fons, Mariano López, Rafael Ramos

Abstract: Many image-processing algorithms require several stages to be processed that cannot be resolved by embedded microprocessors in a reasonable time, due to their high-computational cost. A set of dedicated coprocessors can accelerate the resolution of these algorithms, although the main drawback is the area needed for their implementation. The main advantage of a reconfigurable system is that several coprocessors designed to perform different operations can be mapped on the same area in a time-multiplexed way. This work presents the architecture of an embedded system composed of a microprocessor and a run-time reconfigurable coprocessor, mapped on Spartan-3, the low-cost family of Xilinx FPGAs. Designing reconfigurable systems on Spartan-3 requires much design effort, since unlike higher cost families of Xilinx FPGAs, this device does not officially support partial reconfiguration. In order to overcome this drawback, the paper also describes the main steps used in the design flow to obtain a successful design. The main goal of the presented architecture is to reduce the coprocessor reconfiguration time, as well as accelerate image-processing algorithms. The experimental results demonstrate significant improvement in both objectives. The reconfiguration rate nearly achieves 320 Mb/s which is far superior to the previous related works.

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DOI: 10.3217/jucs-018-20-2748

Authors: Lutz Prechelt

Abstract: In September 1997, J.UCS published an article titled "Why we Need an Explicit Forum for Negative Results" [Prechelt, 1997]. It argued that when a plausible approach for solving a computer science or software engineering problem had failed to work out, it was silly for the scientific system not to publish the attempt iff a useful insight had been gained along the way nevertheless. Due to the strong bias of essentially all Computer Science publication venues towards "successful" research results, it was thus required to call for such negative results explicitly in order to avoid that those results would either be misleadingly disguised as successes or disappear in some closet. The article declared that J.UCS had thus agreed to create the "Forum for Negative Results (FNR)" as a permanent special section of J.UCS.

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DOI: 10.3217/jucs-018-07-0937

Authors: Maurizio Palesi, Rafael Tornero, Juan Orduñna, Vincenzo Catania, Daniela Panno

Abstract: Mainstream electronic designs are realized by Systems-on-Chips (SoCs) that push the limits of integration. The advancement of manufacturing technologies in terms of integration leads us to SoCs with many (e.g., 10-1000) digital units (e.g., processor cores, controllers, storage, application-specific units) that need to be interconnected in an efficient and reliable way. The Network-on-Chip (NoC) design paradigm emerged recently as a promising alternative to classical bus-based communication architectures. Aside from better predictability and lower power consumption, the NoC approach offers greater scalability compared to previous solutions for on-chip communication. The design flow of NoCs include several key issues. Among other parameters, the decision of where cores have to be topologically mapped and also the routing algorithm represent two highly correlated design problems that must be carefully solved for any given application in order to optimize different performance metrics. The strong correlation between the different parameters often makes that the optimization of a given performance metric has a negative effect on a different performance metric. In this paper we propose a new strategy that simultaneously refines the mapping and the routing function to determine the Pareto optimal configurations which optimize average communication delay and routing robustness. The proposed strategy has been applied on both synthetic and real traffic scenarios. The obtained results show how the solutions found by the proposed approach outperforms those provided by other approaches proposed in literature, in terms of both performance and fault tolerance.

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DOI: 10.3217/jucs-018-07-0917

Authors: Luneque Junior, Nadia Nedjah, Luiza Mourelle

Abstract: Network-on-Chip (NoC) have been used as an interesting option in design of communication infrastructures for embedded systems, providing a scalable structure and balancing the communication between cores. Because several data packets can be transmitted simultaneously through the network, an efficient routing strategy must be used in order to avoid congestion delays. In this paper, ant colony algorithms were used to find and optimize routes in a mesh-based NoC. The routing optimization is driven by the minimization of total latency in packets transmission. The simulation results show the effectiveness of the ant colony inspired routing by comparing it with general purpose algorithms for deadlock free routing under different traffic patterns.

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DOI: 10.3217/jucs-018-02-0264

Authors: Joaquin Olivares

Abstract: This paper presents an architecture which is capable of processing variable block size motion estimation (VBSME) and which is able to apply pixel precision reduction techniques in a reconfigurable way. The design has been carried out by using online arithmetic, which allows to process all motion vectors of a block in just one iteration. The system has been implemented on FPGA and just requires 7724 slices, reaching a performance of 55 4CIF frames per second (fps) in full precision and of 72 with 4 bit precision. Results for different search areas 31 x 31, 32 x 32, and 46 x 46 are presented. Using 4bit precision real time processing for HDTVp is achieved. Thanks to the reduced cost and high performance, this architecture is perfect for mobile devices.

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DOI: 10.3217/jucs-016-14-1826

Authors: Václav Dvořák, Petr Mikušek

Abstract: Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways, from hardware to firmware to software. The paper presents a new computer-aided technique that can produce representations of arbiters/allocators in a form of a Multi-Terminal Binary Decision Diagram (MTBDD) with close to minimum cost and width. This diagram can then serve as a prototype for a cascade of multiple-output look-up tables (LUTs) that implements the given function, or for efficient firmware implementation. The technique makes use of iterative decomposition of integer functions of Boolean variables and a variable-ordering heuristic to order variables. The LUT cascades lead directly to the pipelined design, simplify wiring and testing and can compete with the traditional FPGA design in performance and with PLA design in chip area.

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DOI: 10.3217/jucs-014-22-3716

Authors: Naghmeh Karimi, Armin Alaghi, Mahshid Sedghi, Zainalabedin Navabi

Abstract: This paper presents efficient methods for online fault detection and diagnosis of Network-on-Chip (NoC) switches. The fault model considered in this research is a system level fault model based on the generic properties of NoC switch functionality. The proposed method is evaluated by fault simulation in a platform using this system level fault model. The experimental results show that with a relatively low area overhead, a large number of NoC switch faults can be detected and diagnosed.

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DOI: 10.3217/jucs-014-15-2532

Authors: Marcos Paulo Mello Araujo, Nadia Nedjah, Luiza Mourelle

Abstract: Synchronous finite state machines are very important for digital sequential designs. Among other important aspects, they represent a powerful way for synchronizing hardware components so that these components may cooperate adequately in the fulfillment of the main objective of the hardware design. In this paper, we propose an evolutionary methodology to solve one of the problems related to the design of finite state machines. We optimally solve the state assignment NP -complete problem using a quantum inspired evolutionary algorithm. This is motivated by the fact that with an optimal state assignment one can physically implement the state machine using a minimal hardware area and response time.

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DOI: 10.3217/jucs-014-12-1949

Authors: Angelo Gargantini, Elvinia Riccobene, Patrizia Scandurra

Abstract: In this paper, we present a concrete textual notation, called AsmetaL, and a general-purpose simulation engine, called AsmetaS, for Abstract State Machine (ASM) specifications. They have been developed as part of the ASMETA (ASMs mETAmodelling) toolset, which is a set of tools for ASMs based on the metamodelling approach of the Model-driven Engineering. We briefly present the ASMETA framework, and we discuss how the language and the simulator have been developed exploiting the advantages offered by the metamodelling approach. We introduce the language AsmetaL used to write ASM specifications, and we provide the AsmetaL encoding of ASM specifications of increasing complexity. We explain the AsmetaS architecture, its kernel engine, and how the simulator works within the ASMETA tool set. We discuss the features currently supported by the simulator and how it has been validated.

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DOI: 10.3217/jucs-014-10-1678

Authors: Alfredo Rosado-Muñoz, Luis Gomez-Chova, Joan Francés

Abstract: This paper describes the development of an Intellectual Property (IP) core in VHDL able to implement a Multilayer Perceptron (MLP) artificial neural network (ANN) topology with up to 2 hidden layers, 128 neurons, and 31 inputs per neuron. Neural network models are usually developed by using programming languages, such as Matlab®. However, their implementation in configurable logic hardware requires the use of some other tools and hardware description languages, such as as VHDL. For easy migration, a Matlab Graphical User Interface (GUI) to automatically translate the ANN architecture to VHDL code has been developed. In addition, the use of an activation function based on fuzzy logic for the implementation of the MLP neural network simplifies the logic and improves the results. The environment was tested using a typical prediction problem, the Mackey-Glass series, where several ANN topologies were generated, tested and implemented in an FPGA. Results show the excellent agreement between the results provided by the software model and the hardware implementation.

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DOI: 10.3217/jucs-014-03-0481

Authors: Omran Ahmadi, Darrel Hankerson, Francisco Rodríguez-Henríquez

Abstract: We present an algorithm that by using the τ and τ-1 Frobenius operators concurrently allows us to obtain a parallelized version of the classical τ-and-add scalar multiplicationalgorithm for Koblitz elliptic curves. Furthermore, we report suitable irreducible polynomials that lead to efficient implementations of both τ and τ-1, thus showing that our algorithm canbe effectively applied on all the NIST-recommended curves. We also present design details of software and hardware implementations of our procedure. In a two-processor workstation soft-ware implementation, we report experimental data showing that our parallel algorithm is able to achieve a speedup factor of almost 2 when compared with the standard sequential point multipli-cation. In our hardware implementation, the parallel version yields a more modest acceleration of 17% when compared with the traditional point multiplication algorithm. Although the focus ison Koblitz curves, analogous strategies are discussed for other curves, in particular for random curves over binary fields.

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DOI: 10.3217/jucs-013-13-1972

Authors: Shunsuke Sasaki, Tasuku Nishihara, Daisuke Ando, Masahiro Fujita

Abstract: System Dependence Graph (SDG) is a graph representation which shows dependencies among statements / expressions in a design. In this paper, we propose a new HW/SW co-design methodology based on SDG. In our method, any combination of C / C++ / SpecC descriptions is acceptable as input designs so that design functions can be specified flexibly. First, the input descriptions are analyzed and verified with static but partially dynamic program checking methods by traversing SDG. With those methods, large descriptions can be processed. Next, those designs are divided into HW and SW parts. In this step, SDGs are fully utilized to insert parallelism into the designs, and it enables flexible HW/SW partitioning. The HW parts are further optimized and then converted into RTL descriptions by existing behavioral synthesis tools. Finally, the generated RTL descriptions together with the SW parts are compared to the original descriptions in order to make sure that they are logically equivalent. Also, designerspecified properties may be model checked with these final design descriptions. Such formal verifications can be realized by translating those descriptions into Finite State Machine (FSM) type representations and existing formal verifiers. We show two case studies with practical examples to demonstrate the usefulness of our approach.

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DOI: 10.3217/jucs-013-09-1344

Authors: Youren Wang, Zhiqiang Zhang, Jiang Cui

Abstract: It is a difficult problem that using cellular neural network to make up of analog signal processing circuit. This paper presented the architecture of new cellular neural network SCCNN for analog signal processing circuits, designed the neural cell circuit, and developed the evolutionary design method of the SCCNN based on selfadapting genetic algorithm. In the architecture of new cellular neural network SCCNN, each neural cell connects with four neighborhood neural cells, the neural cell circuit and signal transfer line between neural cells are controlled by programmable switches. The validity of the SCCNN architecture and the evolutionary design method are verified through digital simulation. The experimental results indicate that the SCCNN hardware is a universal cellular neural network for analog signal processing circuit, which can be used to make up of the analog signal amplifier, analog signal filter, digit logic circuit, DAC circuit and so on.

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DOI: 10.3217/jucs-013-07-0959

Authors: José Chaves-González, Miguel A. Vega-Rodríguez, Juan Gómez-Pulido, Juan Sánchez-Pérez

Abstract: This paper presents a project that provides both, to professors and to students, a tool that is useful for studying, teaching and learning how pipelines work and how they can be scheduled in an easy and widespread way. The project is called PipeSim, and features static and dynamic pipelines with a very attractive, dynamic and intuitive interface. It is well known that pipeline and pipeline-scheduling are very relevant concepts in computer science studies and it is very important that students can learn these in an easy and reliable way. The simulator makes easy both working in depth about pipeline scheduling and working slowly paying attention in the different stages of the scheduling. However, we designed the simulator knowing that principal users would be students with no experience, so both the execution and the presentation of the results have been carefully developed. In addition to this, to check the success of PipeSim, a survey has been made among some students that used the simulator. Results reveal that this kind of applications has a great acceptance among students, thought they consider that simulators are complements to the lessons given by the professor and never a substitute for them.

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DOI: 10.3217/jucs-013-05-0661

Authors: Jim Woodcock, Richard Banach

Abstract: This paper overviews the Verification Grand Challenge, a large scale multinationalintiative designed to significantly increase the interoperability, applicability and uptake of formal development techniques. Results to date are reviewed, and next steps are outlined.

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DOI: 10.3217/jucs-013-05-0650

Authors: John Rushby

Abstract: This paper outlines the emergence of formal techniques, explaining why they wereslow to take on an industrially acceptable form. The contemporary scene, in which formal techniques are increasingly packaged within tools usable by a wide variety of engineers, is reviewed,as are the promising prospects for the future.

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DOI: 10.3217/jucs-013-05-0639

Authors: Edmund Clarke, Flavio Lerda

Abstract: This paper introduces model checking, originally conceived for checking finite statesystems. It surveys its evolution to encompass finitely checkable properties of systems with unbounded state spaces, and its application to software and other systems.

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DOI: 10.3217/jucs-013-05-0629

Authors: John Harrison

Abstract: This paper overviews the application of formal verification techniques to hardware ingeneral, and to floating-point hardware in particular. A specific challenge is to connect the usual mathematical view of continuous arithmetic operations with the discrete world, in a credible andverifiable way.

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DOI: 10.3217/jucs-013-05-0593

Authors: Richard Banach

Abstract: This introductory paper gives some historical background to the emergence of formalmethods, overviews what subsequently happened, and surveys prospects for the future. Brief introductions to the remaining papers in the Special Issue are given.

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DOI: 10.3217/jucs-013-03-0440

Authors: José Fernández-Pérez, Francisco Sánchez-Fernández, Ricardo Carmona-Galán

Abstract: This paper presents a survey of the characteristics of a vision system implemented in a reconfigurable/programmable chip (FPGA). System limitations and performance have been evaluated in order to derive specifications and constraints for further vision system synthesis. The system hereby reported has a conventional architecture. It consists in a central microprocessor (CPU) and the necessary peripheral elements for data acquisition, data storage and communications. It has been designed to stand alone, but a link to the programming and debugging tools running in a digital host (PC) is provided. In order to alleviate the computational load of the central microprocessor, we have designed a visual co-processor in charge of the low-level image processing tasks. It operates autonomously, commanded by the CPU, as another system peripheral. The complete system, without the sensor, has been implemented in a single reconfigurable chip as a SOPC. The incorporation of a dedicated visual co-processor, with specific circuitry for low-level image processing acceleration, enhances the system throughput outperforming conventional processing schemes. However, time-multiplexing of the dedicated hardware remains a limiting factor for the achievable peak computing power. We have quantified this effect and sketched possible solutions, like replication of the specific image processing hardware.

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DOI: 10.3217/jucs-013-03-0419

Authors: Rui M. M. Rodrigues, João M. P. Cardoso

Abstract: Sequences of data-dependent tasks, each one traversing large data sets, exist in many applications (such as video, image and signal processing applications). Those tasks usually perform computations (with loop intensive behavior) and produce new data to be consumed by subsequent tasks. This paper shows a scheme to pipeline sequences of data-dependent loops, in such a way that subsequent loops can start execution before the completion of the previous ones, which achieves performance improvements. It uses a hardware scheme with decoupled and concurrent data-path and control units that start execution at the same time. The communication of array elements between two loops in sequence is performed by special buffers with a data-driven, fine-grained scheme. Buffer elements are responsible to flag the availability of each array element requested by a subsequent loop (i.e., a ready protocol is used to trigger the execution of operations in the succeeding loop). Thus, the control execution of following loops is also orchestrated by data availability (in this case at the array element grain) and out-of-order produced-consumed pairs are permitted. The concept has been applied using Nau, a compiler infrastructure to map algorithms described in Java onto FPGAs. This paper presents very encouraging results showing important performance improvements and buffer size reductions for a number of benchmarks.

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DOI: 10.3217/jucs-013-03-0388

Authors: María del Carmen Peréz, Jesús Ureña, Álvaro Hernández, Carlos Marziani, Ana Jiménez, William Marnane

Abstract: Some sensor systems are characterized by multiple simultaneous aperiodic emissions, with low signal-to-noise ratio and asynchronous detection. In these systems, complementary sets of sequences can be used to encode emissions, due to their suitable auto-correlation and cross-correlation properties. The transmission of a complementary set can be accomplished by interleaving the sequences of the set, generating a macro-sequence which is easily transmitted by a BPSK modulation. The detection of the macrosequence can be performed by means of efficient correlation algorithms with a notably decreased computational load and hardware complexity. This work presents a new hardware design in configurable logic of an efficient correlator for macrosequences generated from complementary sets of sequences. A generic implementation has been achieved, so the configuration can be changed according to the requirements of the application. The developed correlator has been tested in an ultrasonic pulse compression system in which real-time is needed. However, it is applicable in any multi-sensor or communication system where the goal is to make simultaneous emissions from different independent sources, minimizing mutual interference.

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DOI: 10.3217/jucs-013-03-0377

Authors: Susana Ortega-Cisneros, Juan Raygoza-Panduro, Alberto de la Mora Gálvez

Abstract: The development of processors with full custom technology has some disadvantages, such as the time used to design the processors and the cost of the implementation. In this article we used the programmable circuits FPGA such as an option of low cost for the development and implementation of Self-Timed (ST) systems. In addition it describes the architecture and the modules that compose the Asynchronous Microprocessor of Centralized Control (AMCC), and reviews the results of the occupation in the implementation of the FPGA. The operation of this processor only requires of an external pulse to the input of the first asynchronous control block, and with this pulse the sequence of request-recognition of the control unit begins, that it activates the cycle search and it begins the process of execution of the instructions, without the need of having a clock feeding the system. Once concluded the program, the microprocessor stops and include inherently the stoppable clock feature; i.e., circuit is stopped if it is not required (minimal dynamic consumption). Until it is activated again by an external request signal.

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DOI: 10.3217/jucs-013-03-0349

Authors: Oscar Pérez, Yves Berviller, Camel Tanougast, Serge Weber

Abstract: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining and dynamic total reconfiguration (DTR). The originality of our implementation is that it computes sequentially in the FPGA the Key and Cipher part of the AES algorithm. This dynamic reconfiguration implementation allows a good optimization of logic resources with a high throughput. This architecture employs only 11619 slices allowing a considerable economy of the resources and reaching a maximum throughput of 44 Gbps.

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DOI: 10.3217/jucs-012-05-0499

Authors: Luis Antonio Brasil Kowada, Renato Portugal, Celina Miraglia Herrera de Figueiredo

Abstract: Karatsuba discovered the first algorithm that accomplishes multiprecision integer multiplication with complexity below that of the grade-school method. This algorithm is implemented nowadays in computer algebra systems using irreversible logic. In this paper we describe reversible circuits for the Karatsuba's algorithm and analyze their computational complexity. We discuss garbage disposal methods and compare with the well known Bennett's schemes. These circuits can be used in reversible computers which have the advantage of being very efficient in terms of energy consumption. The algorithm can also be used in quantum computers and is an improvement of previous circuits for the same purpose described in the literature.

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DOI: 10.3217/jucs-012-04-0432

Authors: Tonio Biondi, Angelo Ciccazzo, Vincenzo Cutello, Santo Antona, Giuseppe Nicosia, Salvatore Spinella

Abstract: The paper concerns the design of evolutionary algorithms and pattern search methods on two circuit design problems: the multi-objective optimization of an Operational Transconductance Amplifier and of a fifth-order leapfrog filter. The experimental results obtained show that evolutionary algorithms are more robust and effective in terms of the quality of the solutions and computational effort than classical methods. In particular, the observed Pareto fronts determined by evolutionary algorithms has a better spread of solutions with a larger number of nondominated solutions when compared to the classical multi-objective techniques.

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DOI: 10.3217/jucs-012-04-0408

Authors: Ajith Abraham, Crina Grosan

Abstract: This paper presents three variants of Genetic Programming (GP) approaches for intelligent online performance monitoring of electronic circuits and systems. Reliability modeling of electronic circuits can be best performed by the stressor — susceptibility interaction model. A circuit or a system is considered to be failed once the stressor has exceeded the susceptibility limits. For on-line prediction, validated stressor vectors may be obtained by direct measurements or sensors, which after pre-processing and standardization are fed into the GP models. Empirical results are compared with artificial neural networks trained using backpropagation algorithm and classification and regression trees. The performance of the proposed method is evaluated by comparing the experiment results with the actual failure model values. The developed model reveals that GP could play an important role for future fault monitoring systems.

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DOI: 10.3217/jucs-012-04-0395

Authors: Nadia Nedjah, Luiza Mourelle

Abstract: In this paper, we propose a methodology based on genetic programming to automatically generate hardware designs of substitution boxes necessary for many cryptosystems such as DES encryption system. We aim at evolving minimal hardware specifications, which minimise both space (i.e. required gate number), response time (i.e. encryption and decryption time) and dissipated power. We compare our results against existing and well-known designs, which were produced by human designers using conventional methods.

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DOI: 10.3217/jucs-012-04-0370

Authors: Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi

Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components, mixed-signal I/O cores) in a single silicon die. The large number of resources that have to communicate makes the use of interconnection systems based on shared buses inefficient. One way to solve the problem of on-chip communications is to use a Network-on-Chip (NoC)-based communication infrastructure. Such interconnection systems offer new degrees of freedom, exploration of which may reveal significant optimization possibilities: the possibility of arranging the computing and storage resources in an NoC, for example, has a great impact on various performance indexes. The paper addresses the problem of topological mapping of intellectual properties (IPs) on the tiles of a mesh-based NoC architecture. The aim is to obtain the Pareto mappings that maximize performance and minimize power dissipation. We propose a heuristic technique based on evolutionary computing to obtain an optimal approximation of the Pareto-optimal front in an efficient and accurate way. At the same time, two of the most widely-known approaches to mapping in mesh­based NoC architectures are extended in order to explore the mapping space in a multi-criteria mode. The approaches are then evaluated and compared, in terms of both accuracy and efficiency, on a platform based on an event-driven trace-based simulator which makes it possible to take account of important dynamic effects that have a great impact on mapping. The evaluation performed on both synthesized traffic and real applications (an MPEG-4 codec) confirms the efficiency, accuracy and scalability of the proposed approach.

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DOI: 10.3217/jucs-012-03-0328

Authors: Jorge Portilla, Angel De Castro, Eduardo Torre, Teresa Riesgo

Abstract: The growth of sensor networks during the last years is a fact and within this field, wireless sensor networks are growing particularly as there are many applications that demand the use of many nodes, even hundreds or thousands. More and more applications are emerging to solve several problems in data acquisition and control in different environments, taking advantage of this technology. In this context, hardware design of the sensor network node becomes critical to satisfy the hard constraints imposed by wireless sensor networks, like low power consumption, low size and low cost. Moreover, these nodes must be capable of sensing, processing and communicating physical parameters, becoming true smart sensors in a network. With this goal in mind, we propose a modular architecture for the nodes, composed of four layers: communication, processing, power supply and sensing. The purpose is to minimize the redesign effort as well as to make the node flexible and adaptable to many different applications. In a first prototype of the node, we present a node with a mixed design based on a microcontroller and an FPGA for the processing layer and Bluetooth technology for communications.

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DOI: 10.3217/jucs-011-07-1135

Authors: Mary Sheeran

Abstract: This paper aims to explain why I am still fascinated by the use of functional languages in hardware design. I hope that some readers will be tempted to tackle some of the hard problems that I outline in the final section. In particular, I believe that programming language researchers have much to contribute to the field of hardware design.

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DOI: 10.3217/jucs-011-06-0916

Authors: Fei He, Lerong Cheng, Guowu Yang, Xiaoyu Song, Ming Gu, Jiaguang Sun

Abstract: Routing space estimation plays a crucial role in design automation of digital systems. We investigate the problem of estimating upper bounds for global routing of two-terminal nets in two-dimensional arrays. We show the soundness of the bounds for both wiring space and total wire-length estimation.

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DOI: 10.3217/jucs-010-12-1655

Authors: John Franco, Michal Kouril, John Schlipf, Sean Weaver, Michael Dransfield, W. Vanfleet

Abstract: Recent work has shown the value of using propositional SAT solvers, as opposed to pure BDD solvers, for solving many real-world Boolean Satisfiability problems including Bounded Model Checking problems (BMC). We propose a SAT solver paradigm which combines the use of BDDs and search methods to support efficient implementation of complex search heuristics and effective use of early (preeprocessor) learning. We implement many of these ideas in software called SBSAT. We show that SBSAT solves many of the benchmarks tested competitively or substantially faster than state-of-the-art SAT solvers. SBSAT differs from standard propositional SAT solvers by working directly with non-CNF propositional input, its input format is BDDs. This allows some BDD-style processing to be used as a preprocessing tool. After preprocessing, the BDDs are transformed into state machines (different state machines than the ones used in the original model checking problem) and a good deal of lookahead information is precomputed and memoized. This provides for fast implementation of a new form of look ahead, called local-function-complete lookahead (contrasting with the depth-first lookahead of zChaff [Moskewicz et al. 01] and the breadth-first lookahead of Prover [Stålmarck 94]). SBSAT provides a choice of search heuristics, allowing users to exploit domain-specific experience. We describe SBSAT in this paper. We use SBSAT in conjunction with the tool bmc from Carnegie Mellon to translate a bounded model checking problem to classical propositional logic and then use SBSAT to solve the bmc output. We show this approach is faster than the now traditional approach of translating the bmc output to CNF clauses and using a CNF-based SAT solver, such as zChaff. The work continues that of [Franco et al. 01] and [Franco et al. 04].

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DOI: 10.3217/jucs-010-12-1629

Authors: Feng Lu, Li-C. Wang, John Moondanos, Ziyad Hanna

Abstract: We propose two heuristics, implicit learning and explicit learning, that utilize circuit topological information and signal correlations to derive conflict clauses that could efficiently prune the search space for solving circuit based SAT problem instances. We implemented a circuit-SAT solver SC-C-SAT based on the proposed heuristics and the concepts used in other state-of-the-art SAT solvers. For solving unsatisfiable circuit examples and for solving difficult circuit-based problems at Intel, our solver is able to achieve speedup of one order of magnitude over other state-of-the-art SAT solvers that do not use the heuristics.

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DOI: 10.3217/jucs-010-12-1597

Authors: Rajat Arora, Michael Hsiao

Abstract: We propose a novel technique to improve SAT-based Combinational Equivalence Checking (CEC). The idea is to perform a low-cost preprocessing that will statically induce global signal relationships into the original CNF formula of the miter circuit under verification, and hence reduce the complexity of the SAT instance. This efficient and effective preprocessing quickly builds up the implication graph for the miter circuit under verification, yielding a large set of direct, indirect and extended backward implications. These two-node implications spanning the entire circuit are converted into binary clauses, and they are added to the miter CNF formula. The added clauses constrain the search space of the SAT solver and provide correlation among the different variables, which enhances the Boolean Constraint Propagation (BCP). Experimental results on large and difficult ISCAS'85, ISC AS'89 (full scan) and ITC'99 (full scan) CEC instances show that our approach is independent of the state-of-the-art SAT solver used, and that the added clauses help to achieve not eworthy speedup for each of the cases. Also, comparison with Hyper-Resolution (Hypre), Non-Increasing Variable Elimination Resolution (NIVER) and the propositional formula checker HeerHugo, suggests that our technique is more powerful, yielding non-trivial clauses that significantly simplify the SAT instance complexity.

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DOI: 10.3217/jucs-010-02-0120

Authors: Bernhard Rinner, Martin Schmid, Reinhold Weiss

Abstract: In this paper we present PEPSY, a novel prototyping environment for multi-DSP systems, with the primary goal to support the design and implementation of parallel digital signal processing (DSP) applications subject to various design constraints. Given a specification of the prototyping problem in the form of an application model, a hardware model and mapping constraints, PEPSY automatically maps and schedules the DSP application onto the multi-processor system and synthesizes the complete code for each processor. A detailed performance model of the parallel application is an integral part of PEPSY. Important performance parameters such as computation and communication times as well as memory consumption can be estimated prior to the implementation. PEPSY not only solves the standard mapping and scheduling problem, but it is also able to explore various important design goals for embedded systems and DSP applications such as minimizing memory and power consumption and enforcing the timeliness of tasks. Two complex case studies demonstrate the feasibility of our prototyping environment.

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DOI: 10.3217/jucs-009-08-0795

Authors: Nélio Muniz Mendes Alves, Sérgio Schneider

Abstract: This paper describes an ongoing implementation of an embedded hardware description language (HDL) using Haskell as a host language. Traditionally, functional HDL s are made using lazy lists to model signals, so circuits are functions from lists of input values to lists of output values. We use another known approach for embedded languages, in which circuits are data structures rather than functions. This style of implementation permits one to inspect the structure of the circuit, allowing one to perform different interpretations for the same description. The approach we present can also be applied to other domain-specific embedded languages. We provide an elegant implementation of memories and a set of new signal types.

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DOI: 10.3217/jucs-009-02-0120

Authors: Andreas Krebs, Jürgen Ruf

Abstract: Verification and validation are the major tasks during the design of digital hardware/software systems. Often more than 70% of the development time is spent for locating and correcting errors in the design. Therefore, many techniques have been developed to support the debugging process. Recently, simulation and test methods have been accompanied by formal methods such as equivalence checking and property checking. However, their industrial applicability is currently restricted to small or medium sized designs or to a specific phase in the design process. Therefore, simulation is still the most commonly applied verification technique. In this paper, we present a method for asserting temporal properties during simulation and also during emulation of hardware prototypes. The properties under verification are efficiently translated into an intermediate language (of a virtual machine). This intermediate representation can then be interpreted during simulation. We may also produce executable checkers running in parallel to the simulation. Furthermore, we are able to translate the properties into synthesizable hardware modules which can then be used during system emulation on FPGA-based emulators or as self test components checking the functionality during the lifetime of the system.

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DOI: 10.3217/jucs-007-11-1088

Authors: Charles Wallace, Guy Tremblay, Jose Amaral

Abstract: We use the Abstract State Machine methodology to give formal operational semantics for the Location Consistency memory model and cache protocol. With these formal models, we prove that the cache protocol satisfies the memory model, but in a way that is strictly stronger than necessary, disallowing certain behavior allowed by the memory model.

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DOI: 10.3217/jucs-006-10-1015

Authors: Paraskevas Evripidou, Costas Kyriacou

Abstract: This paper presents the Data Driven Network Of Workstations (D

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DOI: 10.3217/jucs-006-10-0908

Authors: Lucian Codrescu, D. Wills

Abstract: A dynamic speculative multithreaded processor automatically extracts thread level parallelism from sequential binary applications without software support. The hardware is responsible for partitioning the program into threads and managing inter-thread dependencies. Current published dynamic thread partitioning algorithms work by detecting loops, procedures, or partitioning at fixed intervals. Research has thus far examined these algorithms in isolation from one another. This paper makes two contributions. First, it quantitatively compares different dynamic partitioning algorithms in the context of a fixed microarchitecture. The architecture is a single-chip shared memory multiprocessor enhanced to allow thread and value speculation. Second, this paper presents a new dynamic partitioning algorithm called MEM-slicing. Insights into the development and operation of this algorithm are presented. The technique is particularly suited to irregular, non-numeric programs, and greatly outperforms other algorithms in this domain. MEM-slicing is shown to be an important tool to enable the automatic parallelization of irregular binary applications. Over SPECint95, an average speedup of 3.4 is achieved on 8 processors.

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DOI: 10.3217/jucs-006-02-0227

Authors: Florent De Dinechin

Abstract: Studying the architectural evolution of mainstream field programmable gate arrays (FPGAs) leads to the following remark: in these circuits, the proportion of silicon devoted to reconfigurable routing is increasing, reducing the proportion of silicon available for computation resources. A quantitative analysis shows that this trend, if pursued, will lead to a widening gap between FPGA performance and VLSI performance. Some prospective solutions to this problem are discussed.

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DOI: 10.3217/jucs-005-06-0323

Authors: Marc Daumas, Claire Finot

Abstract: Floating point expansion is a technique for implementing multiple precision using a processor's floating point unit instead of its integer unit. Research on this subject has arised recently from the observation that the floating point unit becomes a more and more efficient part of modern computers. Many simple arithmetic operators and some very useful geometric operators have already been presented on expansions. Yet previous work included only a very simple division algorithm. We present in this work a new algorithm that allows us to extend the set of geometric operators with Bareiss' determinant on a matrix of size between 3 and 10. Running times with different determinant algorithms on different machines are compared with GMP, a very common multi-precision package.

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DOI: 10.3217/jucs-005-05-0307

Authors: Leo Storme, Alexis Vos, Gerald Jacobs

Abstract: Logic gates with three input bits and three output bits have a privileged position within fundamental computer science: they are a sufficient building block for constructing arbitrary reversible boolean networks and therefore are the key to reversible digital computers. Such computers can, in principle, operate without heat production. As there exist as many as 8! = 40,320 different 3-bit reversible truth tables, the question arises as to which ones to choose as building blocks. Because these gates form a group with respect to the operation "cascading" , we can apply group theoretical tools, in order to make such a choice.

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DOI: 10.3217/jucs-005-05-0288

Authors: Paul Dunne, Paul Leng

Abstract: Demand-driven simulation is an approach to the simulation of digital logic circuits that was proposed, independently, in the work of several authors. Experimental studies of the paradign have indicated that this approach may reduce the time required for simulation, when compared with event-driven techniques. In this paper we present some analytic support for these experimental results by analysing the average number of gates evaluated with a naive demand-driven algorithm for formula evaluation.

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DOI: 10.3217/jucs-003-10-1121

Authors: Bernd Rederlechner, Jörg Keller

Abstract: When adding n-bit 2-th complement numbers, the result can be outside the range representable with n bits. A well-known theorem justifies the common overflow logic: Let a,b {0,1}n be the 2-th complement representations of signed integers [a] and [b], respectively, and let c0 {0, 1} be the carry-in bit. Then, [a] + [b] + c0 {-2n-1,...,2n-1-1} if and only if cn = cn-1 , where ci denotes the carry-bit from position i - 1 to position i when adding the binary numbers a and b. We present a proof of this theorem which is much shorter than previous proofs. This simplification can save valuable time in computer science classes. With a small extension the proof even holds for d-th complement numbers. Although the proof technique is known by some specialists, nobody seems to have written it up. With this note, it is once documented in a precise form, thus avoiding re-invention.

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DOI: 10.3217/jucs-003-09-1074

Authors: Lutz Prechelt

Abstract: Current Computer Science (CS) research is primarily focused on solving engineering problems. Often though, promising attempts for solving a particular problem fail for non-avoidable reasons. This is what I call a negative result: something that should have worked does not. Due to the current CS publication climate such negative results today are usually camouflaged as positive results by non-evaluating or mis-evaluating the research or by redefining the problem to fit the solution. Such publication behavior hampers progress in CS by suppressing some valuable insights, producing spurious understanding, and misleading further research efforts. Specific examples given below illustrate and back up these claims. This paper is the announcement of a (partial) remedy: a permanent publication forum explicitly for negative CS research results, called the Forum for Negative Results, FNR. FNR will be a regular part of J.UCS.

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DOI: 10.3217/jucs-003-02-0086

Authors: Jamaludin Omar, James Noras

Abstract: This paper describes how to design and use a framework of hardware and software for flexible interfacing and prototyping on the PC. The hardware comprises a card with programmable hardware provided by FPGAs, with an interface including DMA block transfer and interrupts. A library of hardware macros is described. Software routines are provided to enable the FPGAs to be programmed and to allow communication between the host PC and the peripheral card. Examples are given to show its use in building and testing designs, so that new applications can be prototyped quickly using a proven and reliable interface.

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DOI: 10.3217/jucs-003-01-0002

Authors: Václav Dvořák

Abstract: Known upper bounds on the number of required nodes (size) in the ordered binary and multiple-valued decision diagram (DD) for representation of logic functions are reviewed and reduced by a small constant factor. New upper bounds are derived for partial logic functions containing don t cares and also for complete Boolean functions specified by Boolean expressions. The evaluation of upper bounds is based on a bottom-up algorithm for constructing efficient ordered DDs developed by the author.

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DOI: 10.3217/jucs-002-06-0474

Authors: Friedrich Heinrichmeyer

Abstract: A possibility to overcome the problem of organizing a diploma-thesis at a distance university with focus on practice in the design of Application Specific Integrated Circuits (ASICs) is presented with the aid of an example. A student of electrical engineering designed a fast arithmetical unit for use in a digital filter with a VHDL software package (ALLIANCE (see [laboratory 1994]) freely distributed on the internet. He did his work at home with a standard personal computer running a free Unix clone (Linux (see [Johnson 1993]) in summer 1993.

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DOI: 10.3217/jucs-002-02-0077

Authors: Dominique Lavenier

Abstract: Biological sequence comparison is a time consuming task on a Von Neuman computer. The addition of dedicated hardware for parallelizing the comparison algorithms results in a reduction of several orders of magnitude in the execution time. This paper presents and compares different dedicated approaches, based on the parallelization of the algorithms on linear arrays of processors.

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DOI: 10.3217/jucs-001-11-0728

Authors: Wolfgang Mayerwieser, Karl Posch, Reinhard Posch, Volker Schindler

Abstract: High speed devices for public key cryptography are of emerging interest. For this reason, the crypto chip was designed. It is an architecture capable of performing fast RSA encryption and other cryptographic algorithms based on modulo multiplication. Besides the modulo multiplication algorithm called FastMM, the reasons for its high computation speed are the As Parallel As Possible (APAP) architecture, as well as the high operation frequency. The crypto chip also contains on-chip RAM and a special-purpose control logic, enabling special features like encrypted key loading. However, this control mechanism influences to some extend testability of the MM data path which is the heart of the chip. For this reason, the crypto chip has been designed to be able to evaluate the behaviour of the pure MM data path. In the following, we describe the strategies used with the crypto chip for testing the MM data path under realistical conditions. In this context, analyzing control signal flow turns out to be the key action.This work has been sponsored as part of the project Nr. P9384PHY "Sichere Kommunikation bei hohen Geschwindigkeiten" by the Austrian Science Foundation.

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DOI: 10.3217/jucs-001-07-0527

Authors: Asger Nielsen, Peter Kornerup

Abstract: We develop a formal account of digit serial number representations by describing them as strings from a language. A prefix of a string represents an int erval approximating a number by enclosure. Standard on-line representations are shown to be a special case of the general digit serial representations. Matrices are introd uced as representations of intervals and a finite-state transducer is used for mapping str ings into intervals. Homographic and bi-homographic functions are used for representing basi c arithmetic operations on digit serial numbers, and finally a digit serial represen tation of floating point numbers is introduced. 1.) This work has been supported by The Danish Research Councils under the grant no.5.21.08.02.

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DOI: 10.3217/jucs-001-07-0484

Authors: Peter Kornerup, David Matula

Abstract: A binary representation of the rationals derived from their continued fraction expansions is described and analysed. The concepts "adjacency", "mediant" and "convergent" from the literature on Farey fractions and continued fractions are suitably extended to provide a foundation for this new binary representation system. Worst case representation-induced precision loss for any real number by a fixed length representable number of the system is shown to be at most 19% of bit word length, with no precision loss whatsoever induced in the representation of any reasonably sized rational number. The representation is supported by a computer arithmetic system implementing exact rational and approximate real computations in an on-line fashion.

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DOI: 10.3217/jucs-001-07-0454

Authors: Jalil Asserrhine, Jean-Marie Chesneaux, Jean-Luc Lamotte

Abstract: Numerical validation of computed results in scientific computation is always an essential problem as well on sequential architecture as on parallel architecture. The probabilistic approach is the only one that allows to estimate the round-off error propagation of the floating point arithmetic on computers. We begin by recalling the basics of the CESTAC method (Controle et Estimation Stochastique des Arrondis de Calculs). Then, the use of the CADNA software (Control of Accuracy and Debugging For Numerical Applications) is presented for numerical validation on sequential architecture. On parallel architecture, we present two solutions for the control of round-off errors. The first one is the combination of CADNA and the PVM library. This solution allows to control round-off errors of parallel codes with the same architecture. It does not need more processors than the classical parallel code. The second solution is represented by the RAPP prototype. In this approach, the CESTAC method is directly parallelized. It works both on sequential and parallel programs. The essential difference is that this solution requires more processors than the classical codes. These different approaches are tested on sequential and parallel programs of multiplication of matrices.

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DOI: 10.3217/jucs-001-07-0439

Authors: Thomas Lynch, Michael Schulte

Abstract: The result of a simple floating-point computation can be in great error, even though no error is signaled, no coding mistakes are in the program, and the computer hardware is functioning correctly. This paper proposes a set of instructions appropriate for a general purpose microprocessor that can be used to improve the credibility and accuracy of numerical computations. Such instructions provide direct hardware support for monitoring events which may threaten computational integrity, implementing floating-point data types of arbitrary precision, and repeating calculations with greater precision. These useful features are obtained by the efficient implementation of high radix on-line arithmetic. The prevalence of super-scalar and VLIW processors makes this approach especially attractive.

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DOI: 10.3217/jucs-001-03-0176

Authors: R. Doran

Abstract: This surveys algorithms and circuits for integer division in special cases. These include division by constants, small divisors, exact divisors, and cases where the divisor and the number base have a special relationship. The related operation of remainder is also covered. Various prior techniques are treated in a common framework. Worked examples are provided together with examples of practical application.

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DOI: 10.3217/jucs-001-03-0162

Authors: Marc Daumas, Christophe Mazenc, Xavier Merrheim, Jean-Michel Muller

Abstract: A new range reduction algorithm, called ModularRange Reduction (MRR), briefly introduced by the authors in [Daumas et al. 1994] is deeply analyzed. It is used to reduce the arguments to exponential and trigonometric function algorithms to be within the small range for which the algorithms are valid. MRR reduces the arguments quickly and accurately. A fast hardwired implementation of MRR operates in time (log(n)), where n is the number of bits of the binary input value. For example, with MRR it becomes possible to compute the sine and cosine of a very large number accurately. Web propose two possible architectures implementing this algorithm.

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DOI: 10.3217/jucs-001-01-0002

Authors: Peter Fenwick

Abstract: High-radix division, developing several quotient bits per clock, is usually limited by the difficulty of generating accurate high-radix quotient digits. This paper describes techniques which allow quotient digits to be inaccurate, but then refine the result. We thereby obtain dividers with slightly reduced performance, but with much simplified logic. For example, a nominal radix-64 divider can generate an average of 4.5 to 5.5 quotient bits per cycle with quite simple digit estimation logic. The paper investigates the technique for radices of 8, 16, 64 and 256, including various qualities of digit estimation, and operation with restricted sets of divisor multiples.

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