Latest Articles from JUCS - Journal of Universal Computer Science Latest 8 Articles from JUCS - Journal of Universal Computer Science https://lib.jucs.org/ Thu, 28 Mar 2024 15:05:49 +0200 Pensoft FeedCreator https://lib.jucs.org/i/logo.jpg Latest Articles from JUCS - Journal of Universal Computer Science https://lib.jucs.org/ A Compiler and Language Support for Designing Mixed-Criticality Applications https://lib.jucs.org/article/71831/ JUCS - Journal of Universal Computer Science 27(8): 894-911

DOI: 10.3897/jucs.71831

Authors: Nermin Kajtazovic, Peter Hödl, Leo Happ Botler

Abstract: Coexistence of software components and functions of different criticality in a single computing platform has challenged the safety community for the past two decades. Despite efforts that have been made so far, dealing with mixed-criticality has still left some room for improvements. One particular concern here is that partitioning of hardware and software resources with regard to criticality (safety related, non-safety related) has direct implications on how safety measures need to be realised. For example, a self-test that must meet certain diagnostic coverage for the microcontroller core by inspecting its instructions, needs to cover only those instructions which are able to affect a safety function. Available software mechanisms and tools are to a certain extent still unable to deal with such a fine-grained selection of resources. In this work, we introduce a compiler extension and language support which enable accurate selection of data based on their criticality. The compiler extension serves to establish detailed traceability between the software code and its representation in runtime memory. With the language support, the individual data elements can be classified based on the desired safety integrity level. As a result, safety measures that operate on data (e.g. Abraham test for SRAM can achieve better coverage. The method has been evaluated and applied to industrial safety controllers. We provide here relevant performance figures and discuss possible applications of the method in other fields.

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Research Article Sat, 28 Aug 2021 10:00:00 +0300
Weather Station IoT Educational Model Using Cloud Services https://lib.jucs.org/article/24151/ JUCS - Journal of Universal Computer Science 26(11): 1495-1512

DOI: 10.3897/jucs.2020.079

Authors: Ján Molnár, Simona Kirešová, Tibor Vince, Dobroslav Kováč, Patrik Jacko, Matej Bereš, Peter Hrabovský

Abstract: IoT technology is gaining more and more popularity in practice, as it collects, processes, evaluates and stores important measured data. The IoT is used every day in the work, in the home or smart houses or in public areas. It realizes the connectivity between real world and digital world which means, that it converts physical quantities of the real world in the form of analog signals into digital numbers stored in clauds. It is essential that students gain practical experience in the design and implementation of the IoT systems during their studies. The article first describes IoT issues and communication protocols used in IoT generally are closer described. Then the design and implementation of an educational model of IoT system - Weather station with the ThingSpeak cloud support is described. The created IoT model interconnects microcontroller programming, sensors and measuring, cloud API interfaces, MATLAB scripts which are useful to analyses the stored data, Windows and Android application developing.

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Research Article Sat, 28 Nov 2020 00:00:00 +0200
Safe Motor Controller in a Mixed-Critical Environment with Runtime Updating Capabilities https://lib.jucs.org/article/22957/ JUCS - Journal of Universal Computer Science 21(2): 177-205

DOI: 10.3217/jucs-021-02-0177

Authors: Jose Gutiérrez-Rivas, Simon Holmbacka, Miguel Míndez-Macías, Wictor Lund, Sebastien Lafond, Johan Lilius, Javier Díaz-Alonso

Abstract: Safety-critical systems and certification standards are the bare essential elements for the development process of avionics, automotive and industrial embedded systems. The necessity of including non-safety capabilities to reduce the price of these systems has resulted in a new type of critical systems, the mixed-criticality ones. These systems should be able to execute safety-critical applications but, at the same time, to run non-safety-critical functionalities without affecting the integrity of the safety-critical tasks. This paper presents a new system architecture which includes safety-critical and non-safety-critical parts in order to form a mixed-criticality system. The system consists of a reliable platform with a dual-core processor (implemented using a FPGA) architecture designed as open-hardware, running two isolated real-time operating systems which are connected through a safe core-to-core communication channel that executes the safety-critical applications. Moreover, the safety-critical system is connected to an external processor, an ARM9, which is used as an external sensing system. The ARM9 runs the non-safety-critical applications and allows the system to insert modifications updating without affecting the safety capabilities of the safety-critical part. This platform is described providing evidences of the isolation between safety-critical (SC) and non-safety-critical (NSC) applications, as well as describing an updating methodology for non-safety-critical applications. This system is validated using a complete and reliable application for safe emergency stop applications for industrial machinery.

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Research Article Sun, 1 Nov 2015 00:00:00 +0200
Design of Arbiters and Allocators Based on Multi-Terminal BDDs https://lib.jucs.org/article/29734/ JUCS - Journal of Universal Computer Science 16(14): 1826-1852

DOI: 10.3217/jucs-016-14-1826

Authors: Václav Dvořák, Petr Mikušek

Abstract: Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways, from hardware to firmware to software. The paper presents a new computer-aided technique that can produce representations of arbiters/allocators in a form of a Multi-Terminal Binary Decision Diagram (MTBDD) with close to minimum cost and width. This diagram can then serve as a prototype for a cascade of multiple-output look-up tables (LUTs) that implements the given function, or for efficient firmware implementation. The technique makes use of iterative decomposition of integer functions of Boolean variables and a variable-ordering heuristic to order variables. The LUT cascades lead directly to the pipelined design, simplify wiring and testing and can compete with the traditional FPGA design in performance and with PLA design in chip area.

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Research Article Wed, 28 Jul 2010 00:00:00 +0300
Quantum-Inspired Evolutionary State Assignment for Synchronous Finite State Machines https://lib.jucs.org/article/29167/ JUCS - Journal of Universal Computer Science 14(15): 2532-2548

DOI: 10.3217/jucs-014-15-2532

Authors: Marcos Paulo Mello Araujo, Nadia Nedjah, Luiza Mourelle

Abstract: Synchronous finite state machines are very important for digital sequential designs. Among other important aspects, they represent a powerful way for synchronizing hardware components so that these components may cooperate adequately in the fulfillment of the main objective of the hardware design. In this paper, we propose an evolutionary methodology to solve one of the problems related to the design of finite state machines. We optimally solve the state assignment NP -complete problem using a quantum inspired evolutionary algorithm. This is motivated by the fact that with an optimal state assignment one can physically implement the state machine using a minimal hardware area and response time.

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Research Article Fri, 1 Aug 2008 00:00:00 +0300
On Pipelining Sequences of Data-Dependent Loops https://lib.jucs.org/article/28758/ JUCS - Journal of Universal Computer Science 13(3): 419-439

DOI: 10.3217/jucs-013-03-0419

Authors: Rui M. M. Rodrigues, João M. P. Cardoso

Abstract: Sequences of data-dependent tasks, each one traversing large data sets, exist in many applications (such as video, image and signal processing applications). Those tasks usually perform computations (with loop intensive behavior) and produce new data to be consumed by subsequent tasks. This paper shows a scheme to pipeline sequences of data-dependent loops, in such a way that subsequent loops can start execution before the completion of the previous ones, which achieves performance improvements. It uses a hardware scheme with decoupled and concurrent data-path and control units that start execution at the same time. The communication of array elements between two loops in sequence is performed by special buffers with a data-driven, fine-grained scheme. Buffer elements are responsible to flag the availability of each array element requested by a subsequent loop (i.e., a ready protocol is used to trigger the execution of operations in the succeeding loop). Thus, the control execution of following loops is also orchestrated by data availability (in this case at the array element grain) and out-of-order produced-consumed pairs are permitted. The concept has been applied using Nau, a compiler infrastructure to map algorithms described in Java onto FPGAs. This paper presents very encouraging results showing important performance improvements and buffer size reductions for a number of benchmarks.

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Research Article Wed, 28 Mar 2007 00:00:00 +0300
Design and Implementation of the AMCC Self-Timed Microprocessor in FPGAs https://lib.jucs.org/article/28750/ JUCS - Journal of Universal Computer Science 13(3): 377-387

DOI: 10.3217/jucs-013-03-0377

Authors: Susana Ortega-Cisneros, Juan Raygoza-Panduro, Alberto de la Mora Gálvez

Abstract: The development of processors with full custom technology has some disadvantages, such as the time used to design the processors and the cost of the implementation. In this article we used the programmable circuits FPGA such as an option of low cost for the development and implementation of Self-Timed (ST) systems. In addition it describes the architecture and the modules that compose the Asynchronous Microprocessor of Centralized Control (AMCC), and reviews the results of the occupation in the implementation of the FPGA. The operation of this processor only requires of an external pulse to the input of the first asynchronous control block, and with this pulse the sequence of request-recognition of the control unit begins, that it activates the cycle search and it begins the process of execution of the instructions, without the need of having a clock feeding the system. Once concluded the program, the microprocessor stops and include inherently the stoppable clock feature; i.e., circuit is stopped if it is not required (minimal dynamic consumption). Until it is activated again by an external request signal.

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Research Article Wed, 28 Mar 2007 00:00:00 +0300
On Dynamic Speculative Thread Partitioning and the MEM-Slicing Algorithm https://lib.jucs.org/article/27717/ JUCS - Journal of Universal Computer Science 6(10): 908-927

DOI: 10.3217/jucs-006-10-0908

Authors: Lucian Codrescu, D. Wills

Abstract: A dynamic speculative multithreaded processor automatically extracts thread level parallelism from sequential binary applications without software support. The hardware is responsible for partitioning the program into threads and managing inter-thread dependencies. Current published dynamic thread partitioning algorithms work by detecting loops, procedures, or partitioning at fixed intervals. Research has thus far examined these algorithms in isolation from one another. This paper makes two contributions. First, it quantitatively compares different dynamic partitioning algorithms in the context of a fixed microarchitecture. The architecture is a single-chip shared memory multiprocessor enhanced to allow thread and value speculation. Second, this paper presents a new dynamic partitioning algorithm called MEM-slicing. Insights into the development and operation of this algorithm are presented. The technique is particularly suited to irregular, non-numeric programs, and greatly outperforms other algorithms in this domain. MEM-slicing is shown to be an important tool to enable the automatic parallelization of irregular binary applications. Over SPECint95, an average speedup of 3.4 is achieved on 8 processors.

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Research Article Sat, 28 Oct 2000 00:00:00 +0300