DOI: 10.3897/jucs.2020.074

Authors: Tibor Vince, Matej Bereš, Irena Kováčová, Ján Molnár, Branislav Fecko, Jozef Dziak, Iveta Tomčiková, Milan Guzan

Abstract: The paper presents analyses of the implementation of IoT in the patent technology of the remote measuring laboratory (VMLab). The technology allows to create a new electrical connection between different devices, where the connection diagram was not defined before. This may be done remotely around the world. To begin with, an application of this technology as a remote measuring laboratory is presented and described. Analyses of the possible application of IoT technology in the Remote Measurement Laboratory (VMLAB) with a final design are also presented. The research focuses on an efficient way to retrieve measured values synchronized over the Internet from multiple measuring devices and controllable devices, without an Ethernet or Wi-Fi interface from the manufacturer. The analyses may also be useful when implementing an additional IoT approach to existing systems.

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DOI: 10.3217/jucs-018-07-0937

Authors: Maurizio Palesi, Rafael Tornero, Juan Orduñna, Vincenzo Catania, Daniela Panno

Abstract: Mainstream electronic designs are realized by Systems-on-Chips (SoCs) that push the limits of integration. The advancement of manufacturing technologies in terms of integration leads us to SoCs with many (e.g., 10-1000) digital units (e.g., processor cores, controllers, storage, application-specific units) that need to be interconnected in an efficient and reliable way. The Network-on-Chip (NoC) design paradigm emerged recently as a promising alternative to classical bus-based communication architectures. Aside from better predictability and lower power consumption, the NoC approach offers greater scalability compared to previous solutions for on-chip communication. The design flow of NoCs include several key issues. Among other parameters, the decision of where cores have to be topologically mapped and also the routing algorithm represent two highly correlated design problems that must be carefully solved for any given application in order to optimize different performance metrics. The strong correlation between the different parameters often makes that the optimization of a given performance metric has a negative effect on a different performance metric. In this paper we propose a new strategy that simultaneously refines the mapping and the routing function to determine the Pareto optimal configurations which optimize average communication delay and routing robustness. The proposed strategy has been applied on both synthetic and real traffic scenarios. The obtained results show how the solutions found by the proposed approach outperforms those provided by other approaches proposed in literature, in terms of both performance and fault tolerance.

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DOI: 10.3217/jucs-018-07-0917

Authors: Luneque Junior, Nadia Nedjah, Luiza Mourelle

Abstract: Network-on-Chip (NoC) have been used as an interesting option in design of communication infrastructures for embedded systems, providing a scalable structure and balancing the communication between cores. Because several data packets can be transmitted simultaneously through the network, an efficient routing strategy must be used in order to avoid congestion delays. In this paper, ant colony algorithms were used to find and optimize routes in a mesh-based NoC. The routing optimization is driven by the minimization of total latency in packets transmission. The simulation results show the effectiveness of the ant colony inspired routing by comparing it with general purpose algorithms for deadlock free routing under different traffic patterns.

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DOI: 10.3217/jucs-014-22-3716

Authors: Naghmeh Karimi, Armin Alaghi, Mahshid Sedghi, Zainalabedin Navabi

Abstract: This paper presents efficient methods for online fault detection and diagnosis of Network-on-Chip (NoC) switches. The fault model considered in this research is a system level fault model based on the generic properties of NoC switch functionality. The proposed method is evaluated by fault simulation in a platform using this system level fault model. The experimental results show that with a relatively low area overhead, a large number of NoC switch faults can be detected and diagnosed.

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DOI: 10.3217/jucs-012-04-0370

Authors: Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi

Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components, mixed-signal I/O cores) in a single silicon die. The large number of resources that have to communicate makes the use of interconnection systems based on shared buses inefficient. One way to solve the problem of on-chip communications is to use a Network-on-Chip (NoC)-based communication infrastructure. Such interconnection systems offer new degrees of freedom, exploration of which may reveal significant optimization possibilities: the possibility of arranging the computing and storage resources in an NoC, for example, has a great impact on various performance indexes. The paper addresses the problem of topological mapping of intellectual properties (IPs) on the tiles of a mesh-based NoC architecture. The aim is to obtain the Pareto mappings that maximize performance and minimize power dissipation. We propose a heuristic technique based on evolutionary computing to obtain an optimal approximation of the Pareto-optimal front in an efficient and accurate way. At the same time, two of the most widely-known approaches to mapping in mesh­based NoC architectures are extended in order to explore the mapping space in a multi-criteria mode. The approaches are then evaluated and compared, in terms of both accuracy and efficiency, on a platform based on an event-driven trace-based simulator which makes it possible to take account of important dynamic effects that have a great impact on mapping. The evaluation performed on both synthesized traffic and real applications (an MPEG-4 codec) confirms the efficiency, accuracy and scalability of the proposed approach.

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