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        <title>Latest Articles from JUCS - Journal of Universal Computer Science</title>
        <description>Latest 3 Articles from JUCS - Journal of Universal Computer Science</description>
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            <title>Latest Articles from JUCS - Journal of Universal Computer Science</title>
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		    <title>PSO-Based Feature Selection for Arabic Text Summarization</title>
		    <link>https://lib.jucs.org/article/23654/</link>
		    <description><![CDATA[
					<p>JUCS - Journal of Universal Computer Science 21(11): 1454-1469</p>
					<p>DOI: 10.3217/jucs-021-11-1454</p>
					<p>Authors: Ahmed Al-Zahrani, Hassan Mathkour, Hassan Abdalla</p>
					<p>Abstract: Feature-based approaches play an important role and are widely applied in extractive summarization. In this paper, we use particle swarm optimization (PSO) to evaluate the effectiveness of different state-of-the-art features used to summarize Arabic text. The PSO is trained on the Essex Arabic summaries corpus data to determine the best particle that represents the most appropriate simple/combination of eight informative/structure features used regularly by Arab summarizers. Based on the elected features and their relevant weights in each PSO iteration, the input text sentences are scored and ranked to extract the top ranking sentences in the form of an output summary. The output summary is then compared with a reference summary using the cosine similarity function as the fitness function. The experimental results illustrate that Arabs summarize texts simply, focusing on the first sentence of each paragraph.</p>
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		    <category>Research Article</category>
		    <pubDate>Sun, 1 Nov 2015 00:00:00 +0000</pubDate>
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		    <title>Pipeline-scheduling Simulator for Educational Purpose</title>
		    <link>https://lib.jucs.org/article/28822/</link>
		    <description><![CDATA[
					<p>JUCS - Journal of Universal Computer Science 13(7): 959-969</p>
					<p>DOI: 10.3217/jucs-013-07-0959</p>
					<p>Authors: José Chaves-González, Miguel A. Vega-Rodríguez, Juan Gómez-Pulido, Juan Sánchez-Pérez</p>
					<p>Abstract: This paper presents a project that provides both, to professors and to students, a tool that is useful for studying, teaching and learning how pipelines work and how they can be scheduled in an easy and widespread way. The project is called PipeSim, and features static and dynamic pipelines with a very attractive, dynamic and intuitive interface. It is well known that pipeline and pipeline-scheduling are very relevant concepts in computer science studies and it is very important that students can learn these in an easy and reliable way. The simulator makes easy both working in depth about pipeline scheduling and working slowly paying attention in the different stages of the scheduling. However, we designed the simulator knowing that principal users would be students with no experience, so both the execution and the presentation of the results have been carefully developed. In addition to this, to check the success of PipeSim, a survey has been made among some students that used the simulator. Results reveal that this kind of applications has a great acceptance among students, thought they consider that simulators are complements to the lessons given by the professor and never a substitute for them.</p>
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		    <category>Research Article</category>
		    <pubDate>Sat, 28 Jul 2007 00:00:00 +0000</pubDate>
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		    <title>The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation</title>
		    <link>https://lib.jucs.org/article/28747/</link>
		    <description><![CDATA[
					<p>JUCS - Journal of Universal Computer Science 13(3): 349-362</p>
					<p>DOI: 10.3217/jucs-013-03-0349</p>
					<p>Authors: Oscar Pérez, Yves Berviller, Camel Tanougast, Serge Weber</p>
					<p>Abstract: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining and dynamic total reconfiguration (DTR). The originality of our implementation is that it computes sequentially in the FPGA the Key and Cipher part of the AES algorithm. This dynamic reconfiguration implementation allows a good optimization of logic resources with a high throughput. This architecture employs only 11619 slices allowing a considerable economy of the resources and reaching a maximum throughput of 44 Gbps.</p>
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			]]></description>
		    <category>Research Article</category>
		    <pubDate>Wed, 28 Mar 2007 00:00:00 +0000</pubDate>
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