Latest Articles from JUCS - Journal of Universal Computer Science Latest 6 Articles from JUCS - Journal of Universal Computer Science https://lib.jucs.org/ Fri, 29 Mar 2024 06:55:18 +0200 Pensoft FeedCreator https://lib.jucs.org/i/logo.jpg Latest Articles from JUCS - Journal of Universal Computer Science https://lib.jucs.org/ All-Pairs Shortest Paths Algorithm for Regular 2D Mesh Topologies https://lib.jucs.org/article/23669/ JUCS - Journal of Universal Computer Science 22(11): 1437-1455

DOI: 10.3217/jucs-022-11-1437

Authors: Vladimir Ciric, Aleksandar Cvetkovic, Ivan Milentijevic, Oliver Vojinovic

Abstract: Motivated by the large number of vertices that future technologies will put in the front of path-search algorithms, and inspired by highly regular 2D mesh structures that exist in the domain applications, in this paper we propose a new allpairs shortest paths algorithm, for any given regular 2D mesh topology, with complexity Ο(|V|2), where |V| is the number of vertices in the graph. The proposed algorithm can achieve better runtime than other known algorithms at the cost of narrowing the scope of the graphs that it can process to the graphs with regular 2D topology. The algorithm is developed into formalism by algebraic transformations in tropical algebra of the well-known Floyd-Warshall's algorithm. First we prove the equivalency of the Floyd-Warshall's algorithm and its tropical algebraic representation, and put the transformations of the algorithm into the algebraic domain. Secondly, having in mind the structure of the target class of graphs, we transform the original algorithm in the algebraic domain and develop a simple, low-complexity iterative algorithm for all-pairs shortest paths calculation. Decreasing of computational complexity can contribute to better exploitation of the algorithm in the wide range of applications from hardware design in new emerging technologies to big data problems in information technologies.

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Research Article Tue, 1 Nov 2016 00:00:00 +0200
Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph https://lib.jucs.org/article/28919/ JUCS - Journal of Universal Computer Science 13(13): 1972-2001

DOI: 10.3217/jucs-013-13-1972

Authors: Shunsuke Sasaki, Tasuku Nishihara, Daisuke Ando, Masahiro Fujita

Abstract: System Dependence Graph (SDG) is a graph representation which shows dependencies among statements / expressions in a design. In this paper, we propose a new HW/SW co-design methodology based on SDG. In our method, any combination of C / C++ / SpecC descriptions is acceptable as input designs so that design functions can be specified flexibly. First, the input descriptions are analyzed and verified with static but partially dynamic program checking methods by traversing SDG. With those methods, large descriptions can be processed. Next, those designs are divided into HW and SW parts. In this step, SDGs are fully utilized to insert parallelism into the designs, and it enables flexible HW/SW partitioning. The HW parts are further optimized and then converted into RTL descriptions by existing behavioral synthesis tools. Finally, the generated RTL descriptions together with the SW parts are compared to the original descriptions in order to make sure that they are logically equivalent. Also, designerspecified properties may be model checked with these final design descriptions. Such formal verifications can be realized by translating those descriptions into Finite State Machine (FSM) type representations and existing formal verifiers. We show two case studies with practical examples to demonstrate the usefulness of our approach.

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Research Article Fri, 28 Dec 2007 00:00:00 +0200
On Pipelining Sequences of Data-Dependent Loops https://lib.jucs.org/article/28758/ JUCS - Journal of Universal Computer Science 13(3): 419-439

DOI: 10.3217/jucs-013-03-0419

Authors: Rui M. M. Rodrigues, João M. P. Cardoso

Abstract: Sequences of data-dependent tasks, each one traversing large data sets, exist in many applications (such as video, image and signal processing applications). Those tasks usually perform computations (with loop intensive behavior) and produce new data to be consumed by subsequent tasks. This paper shows a scheme to pipeline sequences of data-dependent loops, in such a way that subsequent loops can start execution before the completion of the previous ones, which achieves performance improvements. It uses a hardware scheme with decoupled and concurrent data-path and control units that start execution at the same time. The communication of array elements between two loops in sequence is performed by special buffers with a data-driven, fine-grained scheme. Buffer elements are responsible to flag the availability of each array element requested by a subsequent loop (i.e., a ready protocol is used to trigger the execution of operations in the succeeding loop). Thus, the control execution of following loops is also orchestrated by data availability (in this case at the array element grain) and out-of-order produced-consumed pairs are permitted. The concept has been applied using Nau, a compiler infrastructure to map algorithms described in Java onto FPGAs. This paper presents very encouraging results showing important performance improvements and buffer size reductions for a number of benchmarks.

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Research Article Wed, 28 Mar 2007 00:00:00 +0300
Multi-Objective Evolutionary Algorithms and Pattern Search Methods for Circuit Design Problems https://lib.jucs.org/article/28603/ JUCS - Journal of Universal Computer Science 12(4): 432-449

DOI: 10.3217/jucs-012-04-0432

Authors: Tonio Biondi, Angelo Ciccazzo, Vincenzo Cutello, Santo Antona, Giuseppe Nicosia, Salvatore Spinella

Abstract: The paper concerns the design of evolutionary algorithms and pattern search methods on two circuit design problems: the multi-objective optimization of an Operational Transconductance Amplifier and of a fifth-order leapfrog filter. The experimental results obtained show that evolutionary algorithms are more robust and effective in terms of the quality of the solutions and computational effort than classical methods. In particular, the observed Pareto fronts determined by evolutionary algorithms has a better spread of solutions with a larger number of nondominated solutions when compared to the classical multi-objective techniques.

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Research Article Fri, 28 Apr 2006 00:00:00 +0300
On Theoretical Upper Bound for Routing Estimation https://lib.jucs.org/article/28418/ JUCS - Journal of Universal Computer Science 11(6): 916-925

DOI: 10.3217/jucs-011-06-0916

Authors: Fei He, Lerong Cheng, Guowu Yang, Xiaoyu Song, Ming Gu, Jiaguang Sun

Abstract: Routing space estimation plays a crucial role in design automation of digital systems. We investigate the problem of estimating upper bounds for global routing of two-terminal nets in two-dimensional arrays. We show the soundness of the bounds for both wiring space and total wire-length estimation.

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Research Article Tue, 28 Jun 2005 00:00:00 +0300
A Signal Correlation Guided Circuit-SAT Solver https://lib.jucs.org/article/28326/ JUCS - Journal of Universal Computer Science 10(12): 1629-1654

DOI: 10.3217/jucs-010-12-1629

Authors: Feng Lu, Li-C. Wang, John Moondanos, Ziyad Hanna

Abstract: We propose two heuristics, implicit learning and explicit learning, that utilize circuit topological information and signal correlations to derive conflict clauses that could efficiently prune the search space for solving circuit based SAT problem instances. We implemented a circuit-SAT solver SC-C-SAT based on the proposed heuristics and the concepts used in other state-of-the-art SAT solvers. For solving unsatisfiable circuit examples and for solving difficult circuit-based problems at Intel, our solver is able to achieve speedup of one order of magnitude over other state-of-the-art SAT solvers that do not use the heuristics.

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Research Article Tue, 28 Dec 2004 00:00:00 +0200