DOI: 10.3897/jucs.164737

Authors: Leo Buron, Andreas Erbslöh, Gregor Schiele

Abstract: For embedded devices, both memory and computational efficiency are essential due to their constrained resources. However, neural network training remains both computation and memory intensive. Although many existing studies apply quantization schemes to mitigate memory overhead, they often employ stochastic rounding for both inference and gradient computation. Notably, no prior work has explored its advantages exclusively in parameter updates. Here, we in-troduce Quantized Parameter Updates (QPU), which uses stochastic rounding (SQPU) to achieve improved and more stable training outcomes. Our fixed-point quantization scheme quantizes parameters (weights and biases) upon model initialization, conducts high-precision gradient com-putations during training, and applies stochastically quantized updates thereafter. This approach substantially lowers memory usage and enables mostly quantized inference, thereby accelerating calculations. Furthermore, storing quantized inputs for gradient computation reduces memory demands even more. When tested on the FASHION-MNIST dataset, our method matches the Straight-Through Estimator (STE) in performance, delivering 0.92% validation accuracy while consuming just 57% of the memory during training. Accepting a slight 1.5% drop in accuracy yields a 50% memory reduction. Additional techniques include stochastic rounding in inference, the use of higher precision for parameters than for layer outputs to limit overflow, L2 regularization via weight decay, and adaptive learning-rate scheduling for improved optimization across a range of batch sizes.

HTML

PDF

DOI: 10.3897/jucs.164654

Authors: Wolfram Luther, A. J. Han Vinck

Abstract: This volume presents a conference paper selection from the 4th Workshop on Collaborative Technologies and Data Science in Smart City Applications (CODASSCA 2024): Data Science and Reliable Machine Learning, held in Yerevan, Armenia, October 3-6, 2024, https://codassca2024.aua.am/. The special issues guest editors invited five groups of authors from Armenia, Chile, Germany, the UK, and the USA to submit enlarged versions of their CODASSCA 2024 papers There was also a J.UCS open call so that any author could submit papers on the highlighted subjects. The invitation to review the 16 contributions received was accepted by 16 experts, and, after three rounds, seven articles were finally accepted for publication in the special issue.

HTML

PDF

DOI: 10.3897/jucs.123539

Authors: Kiran K A, Jaison Jacob

Abstract: Network-on-chip (NoC) architectures have emerged as a potential solution for facilitating communication between processing elements (PEs) in modern multi-core systems. The design and optimization of NoC architectures are critical for achieving efficient communication, reduced energy consumption, and improved overall system performance. In this study, we investigate and compare the performance of two prominent optimization algorithms, like Genetic Algorithm (GA) and CastNet Algorithm, for 2D and 3D mesh NoC architectures. The study’s objective is to estimate these algorithms’ effectiveness in optimizing communication cost, communication energy, and CPU run time in both 2D and 3D mesh NoC architectures. Performance metrics such as communication cost, communication energy consumption, and CPU run time are measured and compared between the two algorithms and carried out on real and custom benchmark applications like MWD, VOPD and MPEG4.

HTML

PDF

DOI: 10.3217/jucs-019-03-0301

Authors: Enrique Cantó, Mariano Fons, Francesc Fons, Mariano López, Rafael Ramos

Abstract: Many image-processing algorithms require several stages to be processed that cannot be resolved by embedded microprocessors in a reasonable time, due to their high-computational cost. A set of dedicated coprocessors can accelerate the resolution of these algorithms, although the main drawback is the area needed for their implementation. The main advantage of a reconfigurable system is that several coprocessors designed to perform different operations can be mapped on the same area in a time-multiplexed way. This work presents the architecture of an embedded system composed of a microprocessor and a run-time reconfigurable coprocessor, mapped on Spartan-3, the low-cost family of Xilinx FPGAs. Designing reconfigurable systems on Spartan-3 requires much design effort, since unlike higher cost families of Xilinx FPGAs, this device does not officially support partial reconfiguration. In order to overcome this drawback, the paper also describes the main steps used in the design flow to obtain a successful design. The main goal of the presented architecture is to reduce the coprocessor reconfiguration time, as well as accelerate image-processing algorithms. The experimental results demonstrate significant improvement in both objectives. The reconfiguration rate nearly achieves 320 Mb/s which is far superior to the previous related works.

HTML

XML

PDF

DOI: 10.3217/jucs-018-20-2748

Authors: Lutz Prechelt

Abstract: In September 1997, J.UCS published an article titled "Why we Need an Explicit Forum for Negative Results" [Prechelt, 1997]. It argued that when a plausible approach for solving a computer science or software engineering problem had failed to work out, it was silly for the scientific system not to publish the attempt iff a useful insight had been gained along the way nevertheless. Due to the strong bias of essentially all Computer Science publication venues towards "successful" research results, it was thus required to call for such negative results explicitly in order to avoid that those results would either be misleadingly disguised as successes or disappear in some closet. The article declared that J.UCS had thus agreed to create the "Forum for Negative Results (FNR)" as a permanent special section of J.UCS.

HTML

XML

PDF

DOI: 10.3217/jucs-014-21-3465

Authors: Ricardo Santos, Rodolfo Azevedo, Guido Araujo

Abstract: This paper1 presents an instruction scheduling algorithm based on the Subgraph Isomorphism Problem. Given a Directed Acyclic Graph (DAG) G1, our algorithm looks for a subgraph G02 in a base graph G2, such that G02 is isomorphic to G1. The base graph G2 represents the arrangement of the processing elements of a high performance computer architecture named 2D-VLIW and G02 is the set of those processing elements required to execute operations in G1. We have compared this algorithm with a greedy list scheduling strategy using programs of the SPEC and MediaBench suites. In our experiments, the average Operation Per Cycle (OPC) and Operations Per Instruction (OPI) achieved by our algorithm are 1.45 and 1.40 times better than the OPC and OPI obtained by the list scheduling algorithm.

HTML

XML

PDF

DOI: 10.3217/jucs-014-10-1678

Authors: Alfredo Rosado-Muñoz, Luis Gomez-Chova, Joan Francés

Abstract: This paper describes the development of an Intellectual Property (IP) core in VHDL able to implement a Multilayer Perceptron (MLP) artificial neural network (ANN) topology with up to 2 hidden layers, 128 neurons, and 31 inputs per neuron. Neural network models are usually developed by using programming languages, such as Matlab®. However, their implementation in configurable logic hardware requires the use of some other tools and hardware description languages, such as as VHDL. For easy migration, a Matlab Graphical User Interface (GUI) to automatically translate the ANN architecture to VHDL code has been developed. In addition, the use of an activation function based on fuzzy logic for the implementation of the MLP neural network simplifies the logic and improves the results. The environment was tested using a typical prediction problem, the Mackey-Glass series, where several ANN topologies were generated, tested and implemented in an FPGA. Results show the excellent agreement between the results provided by the software model and the hardware implementation.

HTML

XML

PDF

DOI: 10.3217/jucs-013-03-0363

Authors: Javier Díaz, Eduardo Ros, Rafael Rodriguez-Gomez, Begoña Pino

Abstract: Motion estimation from image sequences is a complex problem which requires high computing resources and is highly affected by changes in the illumination conditions in most of the existing approaches. In this contribution we present a high performance system that deals with this limitation. Robustness to varying illumination conditions is achieved by a novel technique that combines a gradient-based optical flow method with a non-parametric image transformation based on the Rank transform. The paper describes this method and quantitatively evaluates its robustness to different illumination changing patterns. This technique has been successfully implemented in a real-time system using reconfigurable hardware. Our contribution presents the computing architecture, including the resources consumption and the obtained performance. The final system is a real-time device capable to computing motion sequences in real-time even in conditions with significant illumination changes. The robustness of the proposed system facilitates its use in multiple potential application fields.

HTML

XML

PDF

DOI: 10.3217/jucs-011-02-0327

Authors: Andrzej Gecow, Mariusz Nowostawski, Martin Purvis

Abstract: Contemporary distributed software systems, exposed to highly unpredictable environments, are reaching extremely high complexity levels. For example, open heterogeneous multi-agent systems that may potentially be spread all around the globe are interacting with different types of dynamically changing web-services and web-technologies. Traditional control-based handling of adaptability may not be suitable any more in such systems. Therefore there is a tendency for exploring different adaptability models inspired by biological phenomena. Biological systems inherently are faced with complexity and unpredictable environments, and they exhibit high levels of ad aptability. In this article, we present a theoretical model of development of complex system, which was built originally by Andrzej Gecow, as a computational model in evolutionary biology. This model represents a generic complex system subjected to long sequences of adaptive changes. The model was used for analysis of development processes and also structural tendencies. By tendencies we mean some phenomena that should be expected in any complex system, subjected to a long development process. Some of these tendencies are not desirable, for example bloat of the system. Some of the phenomena, however, show characteristics of changes that improve the system. These characteristics can be applied to optimisation of self-producing and self-adapting algorithms of self-maintaining complex software systems. The main structural tendencies described in this article are: terminal modifications, terminal majority of additions, and covering (reconstructing within the system itself disappearing environmental signals).

HTML

XML

PDF

DOI: 10.3217/jucs-006-10-1015

Authors: Paraskevas Evripidou, Costas Kyriacou

Abstract: This paper presents the Data Driven Network Of Workstations (D

HTML

XML

PDF

DOI: 10.3217/jucs-006-10-0948

Authors: Krishna Kavi, Joseph Arul, Roberto Giorgi

Abstract: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar and superspeculative architectures. This trend allows for better performance at the expense of an increased hardware complexity and a brute-force solution to the memory-wall problem. Our research substantially deviates from this trend by exploring a simpler, yet powerful execution paradigm that is based on dataflow concepts. A program is partitioned into functional execution threads, which are perfectly suited for our non-blocking multithreaded architecture. In addition, all memory accesses are decoupled from the thread's execution. Data is pre-loaded into the thread's context (registers), and all results are post-stored after the completion of the thread's execution. The decoupling of memory accesses from thread execution requires a separate unit to perform the necessary pre-loads and post-stores, and to control the allocation of hardware thread contexts to enabled threads. The analytical analysis of our architecture showed that we could achieve a better performance than other classical dataflow architectures (i.e., ETS), hybrid models (e.g., EARTH) and decoupled multithreaded architectures (e.g., Rhamma processor). This paper analyzes the architecture using an instruction set level simulator for a variety of benchmark programs. We compared the execution cycles required for programs on SDF with the execution cycles required by the programs on DLX (or MIPS). Then we investigated the expected cache-memory performance by collecting address traces from programs and using a trace-driven cache simulator (Dinero-IV). We present these results in this paper.

HTML

XML

PDF

DOI: 10.3217/jucs-003-09-1074

Authors: Lutz Prechelt

Abstract: Current Computer Science (CS) research is primarily focused on solving engineering problems. Often though, promising attempts for solving a particular problem fail for non-avoidable reasons. This is what I call a negative result: something that should have worked does not. Due to the current CS publication climate such negative results today are usually camouflaged as positive results by non-evaluating or mis-evaluating the research or by redefining the problem to fit the solution. Such publication behavior hampers progress in CS by suppressing some valuable insights, producing spurious understanding, and misleading further research efforts. Specific examples given below illustrate and back up these claims. This paper is the announcement of a (partial) remedy: a permanent publication forum explicitly for negative CS research results, called the Forum for Negative Results, FNR. FNR will be a regular part of J.UCS.

HTML

XML

PDF

DOI: 10.3217/jucs-002-04-0164

Authors: Richard Banach

Abstract: This is the first in a series of papers dealing with the implementation of an extended term graph rewriting model of computation (described by the DACTL language) on a distributed store architecture. In this paper we set out the high level model, and under some simple restrictions, prove an abstract packet store implementation correct modulo garbage. The abstract packet store model is compared to a more realistic and finegrained packet store model, more closely related to the properties of a genuine distributed store architecture, and the differences are used to inspire the definition of the MONSTR sublanguage of DACTL, intended for direct execution on the machine. Various alternative operational semantics for MONSTR are proposed to reflect more closely the finegrained packet store model, and the prospects for establishing correctness are discussed. The detailed treatment of the alternative models, in the context of suitable sublanguages of MONSTR where appropriate, are subjects for subsequent papers.

HTML

XML

PDF