DOI: 10.3897/jucs.175236

Authors: Christian Schlager, Atif Mashkoor

Abstract: The automotive industry increasingly relies on complex embedded systems that inte-grate software, electronic hardware, electromechanical, and mechanical components. To ensure quality, the Automotive Software Process Improvement and Capability Determination (ASPICE) framework has been extended by cybersecurity, which has become a critical concern. Recognizing these risks, the United Nations Economic Commission for Europe (UNECE) introduced Regulation No. 155 in 2021, establishing mandatory provisions for vehicle type approval and cybersecurity management. To address these regulatory demands, ASPICE for Cybersecurity extends the standard ASPICE model with additional processes focused on identifying, analyzing, and mitigating security threats. While the combined assessment of ASPICE and ASPICE for Cybersecurity ensures both process maturity and security compliance, it presents significant challenges for organizations. Conducting separate assessments for ASPICE and ASPICE for Cybersecurity increases time, cost, and organizational workload, as many process areas overlap in scope and evidence. This paper proposes a unified assessment approach designed to evaluate compliance with both ASPICE and ASPICE for Cybersecurity in a single, integrated process. The approach involves systematically mapping equivalent or related process areas across the two models. This approach was applied in an industry case study, demonstrating a reduction in total assessment time and minimizing disruption to development teams. The results indicate that integrated assessments can maintain the rigor and comprehensiveness of separate evaluations while improving efficiency and reducing operational burden.

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DOI: 10.3217/jucs-024-12-1776

Authors: J. Kokila, N. Ramasubramanian, Ravindra Thamma

Abstract: Recent processors are shrinking in size due to the advancement of technology. Reliability is an important design parameter along with power, cost, and performance. The processors need to be fault tolerant to counter reliability challenges. This work proposes a dynamic thermal and voltage management (DTVM) system which ensures a reasonable level of fault tolerance. The fault tolerance system (FTS) identifies and subsequently can forecast temporary failures at run-time. The temporary failures are dynamically estimated on SoC FPGAs for a class of heterogeneous applications. The dynamic priority scheduling based on absolute deadline is adopted to improve the nature of FTS. Experimental results indicate that the failure rate reduces by 7.2% with the variation of 2% and 12% in temperature and voltage respectively.

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DOI: 10.3217/jucs-014-22-3716

Authors: Naghmeh Karimi, Armin Alaghi, Mahshid Sedghi, Zainalabedin Navabi

Abstract: This paper presents efficient methods for online fault detection and diagnosis of Network-on-Chip (NoC) switches. The fault model considered in this research is a system level fault model based on the generic properties of NoC switch functionality. The proposed method is evaluated by fault simulation in a platform using this system level fault model. The experimental results show that with a relatively low area overhead, a large number of NoC switch faults can be detected and diagnosed.

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DOI: 10.3217/jucs-012-04-0408

Authors: Ajith Abraham, Crina Grosan

Abstract: This paper presents three variants of Genetic Programming (GP) approaches for intelligent online performance monitoring of electronic circuits and systems. Reliability modeling of electronic circuits can be best performed by the stressor — susceptibility interaction model. A circuit or a system is considered to be failed once the stressor has exceeded the susceptibility limits. For on-line prediction, validated stressor vectors may be obtained by direct measurements or sensors, which after pre-processing and standardization are fed into the GP models. Empirical results are compared with artificial neural networks trained using backpropagation algorithm and classification and regression trees. The performance of the proposed method is evaluated by comparing the experiment results with the actual failure model values. The developed model reveals that GP could play an important role for future fault monitoring systems.

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DOI: 10.3217/jucs-009-02-0120

Authors: Andreas Krebs, Jürgen Ruf

Abstract: Verification and validation are the major tasks during the design of digital hardware/software systems. Often more than 70% of the development time is spent for locating and correcting errors in the design. Therefore, many techniques have been developed to support the debugging process. Recently, simulation and test methods have been accompanied by formal methods such as equivalence checking and property checking. However, their industrial applicability is currently restricted to small or medium sized designs or to a specific phase in the design process. Therefore, simulation is still the most commonly applied verification technique. In this paper, we present a method for asserting temporal properties during simulation and also during emulation of hardware prototypes. The properties under verification are efficiently translated into an intermediate language (of a virtual machine). This intermediate representation can then be interpreted during simulation. We may also produce executable checkers running in parallel to the simulation. Furthermore, we are able to translate the properties into synthesizable hardware modules which can then be used during system emulation on FPGA-based emulators or as self test components checking the functionality during the lifetime of the system.

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